5M160ZM100A5N Altera, 5M160ZM100A5N Datasheet - Page 9

• Manufacturer Part Number: 5M160ZM100A5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX® Vr

Specifications of 5M160ZM100A5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 160
• Number Of Macrocells: 128
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

MV51001-1.1
Feature Summary
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MAX V Device Handbook
January 2011
The MAX
per footprint versus other CPLDs. Ranging in density from 40 to 2,210 logic elements
(LEs) (32 to 1,700 equivalent macrocells) and up to 271 I/Os, MAX V devices provide
programmable solutions for applications such as I/O expansion, bus and protocol
bridging, power monitoring and control, FPGA configuration, and analog IC
interface.
MAX V devices feature on-chip flash storage, internal oscillator, and memory
functionality. With up to 50% lower total power versus other CPLDs and requiring as
few as one power supply, MAX V CPLDs can help you meet your low power design
requirement.
This chapter contains the following sections:
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The following list summarizes the MAX V device family features:
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“Feature Summary” on page 1–1
“Integrated Software Platform” on page 1–3
“Device Pin-Outs” on page 1–3
“Ordering Information” on page 1–4
Low-cost, low-power, and non-volatile CPLD architecture
Instant-on (0.5 ms or less) configuration time
Standby current as low as 25 µA and fast power-down/reset operation
Fast propagation delay and clock-to-output times
Internal oscillator
Emulated RSDS output support with a data rate of up to 200 Mbps
Emulated LVDS output support with a data rate of up to 304 Mbps
Four global clocks with two clocks available per logic array block (LAB)
User flash memory block up to 8 Kbits for non-volatile storage with up to 1000
read/write cycles
Single 1.8-V external supply for device core
MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V logic levels
Bus-friendly architecture including programmable slew rate, drive strength,
bus-hold, and programmable pull-up resistors
Schmitt triggers enabling noise tolerant inputs (programmable per pin)
®
V family of low cost and low power CPLDs offer more density and I/Os
1. MAX V Device Family Overview
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