AD5542AACPZ-REEL7 Analog Devices Inc, AD5542AACPZ-REEL7 Datasheet - Page 15

• Manufacturer Part Number: AD5542AACPZ-REEL7
• Description: 16bit, 2LSB, 2.7-5.5V With CLR, Vlogic
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5542AACPZ-REEL7

• Design Resources: High Precision Digital-to-Analog Conversion Using the 16-Bit AD5542/1, ADR421, and AD8628 (CN0079) How to Achieve High Precision Voltage Level Setting Using AD5541A/42A (CN0169)
• Settling Time: 1µs
• Number Of Bits: 16
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 6.05mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD5542AACPZ-REEL7; AD5542AACPZ-REEL7TR

THEORY OF OPERATION
The AD5512A/AD5542A are single, 12-/16-bit, serial input,
voltage output DACs. They operate from a single supply
ranging from 2.7 V to 5 V and consume typically 125 µA
with a supply of 5 V. Data is written to these devices in a
12-bit (AD5512A) or 16-bit (AD5542A) word format, via a
3- or 4-wire serial interface. To ensure a known power-up
state, these parts are designed with a power-on reset function.
In unipolar mode, the output is reset to midscale; in bipolar
mode, the output is set to 0 V. Kelvin sense connections for the
reference and analog ground are included on the AD5512A/
AD5542A.
DIGITAL-TO-ANALOG SECTION
The DAC architecture consists of two matched DAC sections.
A simplified circuit diagram is shown in Figure 30. The DAC
architecture of the AD5512A/AD5542A is segmented. The four
MSBs of the 16-bit (AD5542A)/12-bit (AD5512A) data-word
are decoded to drive 15 switches, E1 to E15. Each switch
connects one of 15 matched resistors to either AGND or V
The remaining 12 bits of the data-word drive the S0 to S11
switches of a 12-bit voltage mode R-2R ladder network.
With this type of DAC configuration, the output impedance
is independent of code, while the input impedance seen by
the reference is heavily code dependent. The output voltage is
dependent on the reference voltage, as shown in the following
equation:
where:
D is the decimal data-word loaded to the DAC register.
N is the resolution of the DAC.
For a reference of 2.5 V, the equation simplifies to the following:
This gives a V
with full scale loaded to the DAC.
The LSB size is V
V
REF
V
V
OUT
OUT
2R
=
=
12-BIT R-2R LADDER
2R
V
S0
2
OUT
65
5 .
REF
R
,
2
536
REF
×
of 1.25 V with midscale loaded, and 2.5 V
N
×
D
/65,536.
2R . . . . .
S1 . . . . .
Figure 30. DAC Architecture
D
2R
S11
R
INTO 15 EQUAL SEGMENTS
FOUR MSBs DECODED
2R
E1
2R . . . . .
E2 . . . . .
2R
E15
V
OUT
REF
Rev. 0 | Page 15 of 24
.
SERIAL INTERFACE
The AD5512A/AD5542A are controlled by a versatile 3- or 4-
wire serial interface that operates at clock rates of up to 50 MHz
and is compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards. The timing diagram is shown in Figure 3.
Input data is framed by the chip select input, CS . After a high-
to-low transition on CS , data is shifted synchronously and
latched into the input register on the rising edge of the serial
clock, SCLK. Data is loaded MSB first in 12-bit (AD5512A)
or 16-bit (AD5542A) words. After 12 (AD5512A) or 16
(AD5542A) data bits have been loaded into the serial input
register, a low-to-high transition on CS transfers the contents
of the shift register to the DAC. Data can be loaded to the part
only while CS is low.
The AD5512A/AD5542A have an LDAC function that allows
the DAC latch to be updated asynchronously by bringing LDAC
low after CS goes high. LDAC should be maintained high while
data is written to the shift register. Alternatively, LDAC can be
tied permanently low to update the DAC synchronously. With
LDAC tied permanently low, the rising edge of CS loads the data to
the DAC.
UNIPOLAR OUTPUT OPERATION
These DACs are capable of driving unbuffered loads of 60 kΩ.
Unbuffered operation results in low supply current, typically
300 μA, and a low offset error. The AD5512A/AD5542A
provide a unipolar output swing ranging from 0 V to V
The AD5512A/AD5542A can be configured to output both
unipolar and bipolar voltages. Figure 31 shows a typical
unipolar output voltage circuit. The code table for this
mode of operation is shown in Table 9.
Table 9. AD5542A Unipolar Code Table
DAC Latch Contents
MSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
INTERFACE
SERIAL
0.1µF
CS
DIN
SCLK
LDAC
V
5V
DD
LSB
DGND AGNDF
AD5512A/
AD5542A
Figure 31. Unipolar Output
REFF
2.5V
0.1µF
Analog Output
V
V
V
0 V
REF
REF
REF
10µF
AGNDS
REFS
× (65,535/65,536)
× (32,768/65,536) = ½ V
× (1/65,536)
AD5512A/AD5542A
V
OUT
EXTERNAL
AD820/
OP196
OP AMP
UNIPOLAR
OUTPUT
REF
REF
.