AD5542AACPZ-REEL7 Analog Devices Inc, AD5542AACPZ-REEL7 Datasheet - Page 9

• Manufacturer Part Number: AD5542AACPZ-REEL7
• Description: 16bit, 2LSB, 2.7-5.5V With CLR, Vlogic
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5542AACPZ-REEL7

• Design Resources: High Precision Digital-to-Analog Conversion Using the 16-Bit AD5542/1, ADR421, and AD8628 (CN0079) How to Achieve High Precision Voltage Level Setting Using AD5541A/42A (CN0169)
• Settling Time: 1µs
• Number Of Bits: 16
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 6.05mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD5542AACPZ-REEL7; AD5542AACPZ-REEL7TR

Table 8. AD5542A Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
R
V
AGNDF
AGNDS
REFS
REFF
NC
CS
SCLK
DIN
CLR
LDAC
DGND
INV
V
V
FB
OUT
LOGIC
DD
Description
Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry (Force).
Ground Reference Point for Analog Circuitry (Sense).
Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from
2 V to V
Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from
2 V to V
No Connect.
Logic Input Signal. The chip select signal is used to frame the serial data input.
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40%
and 60%.
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.
When CLR is activated, the DAC register is cleared to the model selectable midscale.
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
input register.
Digital Ground. Ground reference for digital circuitry.
Connection to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op amps inverting
input in bipolar mode.
Logic Power Supply.
Analog Supply Voltage, 5 V ± 10%.
DD
DD
.
.
Figure 6. AD5542A 16-Lead TSSOP Pin Configuration
AGNDS
AGNDF
REFS
REFF
V
R
OUT
NC
CS
FB
1
3
4
5
6
8
2
7
NC = NO CONNECT
Rev. 0 | Page 9 of 24
(Not to Scale)
AD5542A
TOP VIEW
16
15
14
13
12
11
10
9
V
V
INV
DGND
LDAC
CLR
DIN
SCLK
DD
LOGIC
AD5512A/AD5542A