AD5542AACPZ-REEL7 Analog Devices Inc, AD5542AACPZ-REEL7 Datasheet - Page 8

• Manufacturer Part Number: AD5542AACPZ-REEL7
• Description: 16bit, 2LSB, 2.7-5.5V With CLR, Vlogic
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5542AACPZ-REEL7

• Design Resources: High Precision Digital-to-Analog Conversion Using the 16-Bit AD5542/1, ADR421, and AD8628 (CN0079) How to Achieve High Precision Voltage Level Setting Using AD5541A/42A (CN0169)
• Settling Time: 1µs
• Number Of Bits: 16
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 6.05mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD5542AACPZ-REEL7; AD5542AACPZ-REEL7TR

AD5512A/AD5542A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. AD5512A/AD5542A Pin Function Descriptions
16-Lead
LFCSP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 4. AD5512A/AD5542A 16-Lead LFCSP Pin Configuration
Pin No.
NC = NO CONNECT
10-Lead
LFCSP
6
2
3
4
5
7
9
8
1
10
EPAD
(Not to Scale)
AGNDS
AGNDF
REFS
V
OUT
1
4
2
3
Mnemonic
V
AGNDF
AGNDS
REFS
REFF
CS
NC
SCLK
DIN
CLR
LDAC
DGND
INV
V
V
R
REF
GND
Exposed Pad
OUT
LOGIC
DD
FB
VIEW
TOP
Description
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry (Force).
Ground Reference Point for Analog Circuitry (Sense).
Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can
range from 2 V to V
Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can
range from 2 V to V
Logic Input Signal. The chip select signal is used to frame the serial data input.
No Connect.
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be
between 40% and 60%.
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the
rising edge of SCLK.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses
are ignored. When CLR is activated, the DAC register is cleared to the model selectable midscale.
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the
contents of the input register.
Digital Ground. Ground reference for digital circuitry.
Connection to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op
amps inverting input in bipolar mode.
Logic Power Supply.
Analog Supply Voltage, 5 V ± 10%.
Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.
Voltage Reference Input for the DAC. Connect this pin to an external 2.5 V reference. Reference can
range from 2 V to V
Ground.
The exposed pad should be tied to the point of lowest potential, in this case, GND.
10
12
11
9
DGND
LDAC
CLR
DIN
DD
DD
DD
Rev. 0 | Page 8 of 24
.
.
.
Figure 5. AD5542A-1 10-Lead LFCSP Pin Configuration
NOTES
SCLK
1. THE EXPOSED PADDLE SHOULD BE
REF
CLR
DIN
CS
TIED TO THE POINT OF LOWEST
POTENTIAL, IN THIS CASE, GND.
1
2
3
4
5
AD5542A-1
Not to Scale
TOP VIEW
10 GND
9
8
7
6
V
R
INV
V
DD
FB
OUT