AD5542AACPZ-REEL7 Analog Devices Inc, AD5542AACPZ-REEL7 Datasheet - Page 6

• Manufacturer Part Number: AD5542AACPZ-REEL7
• Description: 16bit, 2LSB, 2.7-5.5V With CLR, Vlogic
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5542AACPZ-REEL7

• Design Resources: High Precision Digital-to-Analog Conversion Using the 16-Bit AD5542/1, ADR421, and AD8628 (CN0079) How to Achieve High Precision Voltage Level Setting Using AD5541A/42A (CN0169)
• Settling Time: 1µs
• Number Of Bits: 16
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 6.05mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD5542AACPZ-REEL7; AD5542AACPZ-REEL7TR

AD5512A/AD5542A
TIMING CHARACTERISTICS
V
+125°C, unless otherwise noted.
Table 5.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
SCLK
1
2
3
4
5
6
7
8
9
9
10
11
12
13
Guaranteed by design and characterization, not production tested.
All input signals are specified with t
LOGIC
= 2.7 V to 5.5 V, VDD = 5 V, V
1, 2
LDAC
SCLK
NOTES
CLR
1. FOR AD5542A = DB15.
2. FOR AD5512A = DB11.
DIN
CS
Limit
50
20
10
10
5
7
15
10
7
5
5
15
15
15
15
t
12
R
t
= t
6
F
= 1 ns/V and timed from a voltage level of (V
DB15
DB11
t
t
4
8
REF
t
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
9
1
2
= 2.5 V, V
INH
= 90% of V
t
2
Figure 3. Timing Diagram
Description
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
Data hold time (V
Data hold time (V
LDAC pulsewidth
CS high to LDAC low setup
CS high time between active periods
CLR pulsewidth
Rev. 0 | Page 6 of 24
t
13
t
1
LOGIC
t
3
, V
INL
INL
+ V
= 10% of V
INH
)/2.
t
INH
INH
7
= 90% of V
= 3 V, V
t
5
t
11
LOGIC
t
INL
10
= 0 V)
, AGND = DGND = 0 V, −40°C < T
DD
, V
INL
= 10% of V
DD
)
A
<