AD9863BCPZ-50 Analog Devices Inc, AD9863BCPZ-50 Datasheet
AD9863BCPZ-50
Specifications of AD9863BCPZ-50
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AD9863BCPZ-50 Summary of contents
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FEATURES Receive path includes dual 12-bit, 50 MSPS analog-to-digital converters with internal or external reference Transmit path includes dual 12-bit, 200 MSPS digital-to- analog converters with 1×, 2×, or 4× interpolation and programmable gain control Internal clock distribution block includes ...
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AD9863 TABLE OF CONTENTS Tx Path Specifications...................................................................... 3 Rx Path Specifications...................................................................... 4 Power Specifications......................................................................... 5 Digital Specifications........................................................................ 5 Timing Specifications....................................................................... 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance ...
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Tx PATH SPECIFICATIONS FDAC = 200 MSPS; 4× interpolation; RSET = 4.02 kΩ; differential load resistance of 100 Ω unless otherwise noted. Table 1. Parameter Tx PATH GENERAL Resolution Maximum DAC Update Rate Maximum Full-Scale Output Current Full-Scale Error Gain ...
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AD9863 RX PATH SPECIFICATIONS MSPS; internal reference; differential analog inputs, ADC_AVDD = DVDD = 3.3 V, unless otherwise noted. ADC Table 2. Parameter Rx PATH GENERAL Resolution Maximum ADC Sample Rate Gain Mismatch Error Offset Mismatch Error ...
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POWER SPECIFICATIONS Analog and digital supplies = 3 CLKIN1 Table 3. Parameter POWER SUPPLY RANGE Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Driver Supply Voltage (DRVDD) ANALOG SUPPLY CURRENTS Tx Path (20 mA Full-Scale Outputs) Tx Path ...
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AD9863 TIMING SPECIFICATIONS Table 5. Parameter INPUT CLOCK CLKIN2 Clock Rate (PLL Bypassed) PLL Input Frequency PLL Ouput Frequency TxPATH DATA Setup Time (HD24 Mode, Time Required Before Data Latching Edge) Hold Time (HD24 Mode, Time Required After Data Latching ...
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ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Electrical AVDD Voltage DRVDD Voltage Analog Input Voltage Digital Input Voltage Digital Output Current Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) ESD CAUTION ESD ...
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AD9863 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADC_LO_PWR Table 8. Pin Function Descriptions 1 Pin No. Name 1 SPI_DIO (Interp1) 2 SPI_CLK (Interp0) 3 SPI_SDO (FD/HD) 4 ADC_LO_PWR 5, 31 DVDD, DRVDD 6, 32 DVSS, DRVDD 7, 16, 50, 51, 61 ...
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Pin No. Name 52 REFB 54, 55 VIN+B, VIN−B 56 VREF 57, 58 VIN−A, VIN+A 60 REFT 62 RxPWRDWN 63 TxPWRDWN 64 SPI_CS 1 Underlined pin names and descriptions apply when the device is configured without a serial port ...
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AD9863 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) Figure 4. AD9863 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 2 MHz Tone 0 –10 ...
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FREQUENCY (MHz) Figure 10. AD9863 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 76 MHz Tone 74 71 LOW POWER @ 25MSPS ...
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AD9863 SNR –5 –10 –15 –20 –25 –30 INPUT AMPLITUDE (dBFS) Figure 16. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone SNR Performance vs. Input Amplitude 74 72 ...
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FREQUENCY (MHz) Figure 22. AD9863 Tx Path 1 MHz Single-Tone Output FFT of Tx Path with 20 mA Full-Scale Output into 33 Ω Differential ...
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AD9863 Figure 28 to Figure 33 use the same input data to the Tx path, a 64-carrier OFDM signal over a 20 MHz bandwidth, centered at 20 MHz. The two center carriers are removed from the signal to observe the ...
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Figure 34 to Figure 39 use the same input data to the Tx path, a 256-carrier OFDM signal over a 1.75 MHz bandwidth, centered at 7 MHz. The four center carriers are removed from the signal to observe the in-band ...
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AD9863 Figure 40 to Figure 45 use the same input data to the Tx path, a 256-carrier OFDM signal over a 23 MHz bandwidth, centered at 23 MHz. The four center carriers are removed from the signal to observe the ...
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TERMINOLOGY Input Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of ...
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AD9863 THEORY OF OPERATION SYSTEM BLOCK The AD9863 is targeted to cover the mixed-signal front end needs of multiple wireless communications systems. It features a receive path that consists of dual 12-bit receive ADCs and a transmit path that consists ...
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Rx Path Application Section Adding series resistance between the output of the signal source and the VIN pins reduces the drive requirements placed on the signal source. Figure 47 shows this configuration. AD9863 R SERIES VIN+ C SHUNT VIN– R ...
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AD9863 degradation in SNR at a given full-scale input frequency (f due to aperture jitter (t ), can be calculated with the following A equation: SNR degradation = 20 log [(½)π the equation, the rms aperture ...
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AD9863 offers programmable (via the SPI port), fine (trim) gain and offset adjustment for each DAC. Also included in the AD9863 are a phase-locked loop (PLL) clock multiplier and a 1.2 V band gap voltage reference. With ...
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AD9863 channels and aiding in suppressing LO feedthrough. This is especially useful in image rejection architectures. The 10-bit dc offset control of each DAC can be used independently to pro- vide an offset ±12 ...
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DIGITAL BLOCK The AD9863 digital block allows the device to be configured in various timing and operation modes. The following sec- tions discuss the flexible I/O interfaces, the clock distribution block, and the programming of the device through mode pins ...
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AD9863 Table 11 describes AD9863 pin function (when mode pins are used) relative to I/O mode and for half-duplex modes, whether transmitting or receiving. Table 11. AD9863 Pin Function vs. Interface Mode (No SPI Cases) Mode Name U12 Bus FD ...
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Buffered Tx clock output (from IFACE3 pin) equals 2× the DAC update rate; one rising edge per interleaved Tx sample. Note the following about the Rx path in FD mode: • ADC CLK Div register can be used to ...
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AD9863 The following notes provide a general description of the clone mode configuration. For more information, refer to Table 15. Note the following about the Tx path in clone mode: • Interpolation rate of 2× or 4× can be programmed ...
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Table 14. Mode Pin Names and Descriptions Pin Name Description ADC_LO_PWR ADC Low Power Mode Option. ADC_LO_PWR is latched during the rising edge of RESET. Logic low results in ADC operation at nominal power mode. Logic high results in the ...
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AD9863 Configuring with SPI The flexible interface can be configured with register settings. Using the register allows more device programmability. Table 15 shows the required register writes to configure the AD9863 for FD, optional FD, HD24, optional HD24, HD12, optional ...
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SPI Register Map Registers 0x00 to 0x29 of the AD9863 provide flexible operation of the device. The SPI allows access to many configurable options. Detailed descriptions of the bit functions are found in Table 17. Table 16. Register Map Reg. ...
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AD9863 Table 17. Register Bit Descriptions Register Bit Register 0x00: General Bit 7: SDIO BiDir (Bidirectional) Bit 6: LSB First Bit 5: Soft Reset Register 0x01: Clock Mode Bit 7 to Bit 5: Clk_Mode Bit 2: Enable IFACE2 clkout Bit ...
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Register Bit Bit 6: RxREF (Power-Down) Bit 5: DiffRef (Power-Down) Bit 4: VREF (Power-Down) Registers 0x06/0x07: Rx Path Bit 5: Rx_A Twos Complement/ Rx_B Twos Complement Bit 4: Rx_A Clk Duty/Rx_B Clk Duty Registers 0x08/0x09/0x0A: Rx Path Rx Ultralow Power ...
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AD9863 Register Bit Bit 4: TxPGA Fast Update (Mode) Register 0x13: I/O Configuration Bit 7: Tx Twos Complement Bit 6: Rx Twos Complement Bit 5: Tx Inverse Sample Bit 1, Bit 0: Interpolation Control Register 0x14: I/O Configuration Bit 5: ...
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PROGRAMMABLE REGISTERS The AD9863 contains internal registers that are used to configure the device. A serial port interface provides read/write access to the internal registers. Single-byte or dual-byte transfers are supported, as well as MSB first or LSB first transfer ...
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AD9863 Write Operations The SPI write operation uses the instruction header to config- ure a 1-byte or 2-byte register write using the 2/ 1 byte setting. The instruction byte followed by the register data is written serially into the device ...
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Read Operations The readback of registers can be a single or dual data byte operation. The readback can be configured to use 3-wire or 4-wire and can be formatted with MSB first or LSB first. The instruction header is written ...
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AD9863 CLOCK DISTRIBUTION BLOCK Theory/Description The AD9863 uses a PLL clock multiplier circuit and an internal distribution block to generate all required clocks for various timing configurations. The AD9863 has two independent input clocks, CLKIN1 and CLKIN2. The CLKIN1 is ...
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CLKIN1 CLKIN2 1. ALTERNATE TIMING MODE: REG 0x15, BIT 4 2. PLL MULTIPLICATION SETTING: REG 0x15, BITS 2–0 3. PLL OUTPUT DIVIDE BY 5; REG 0x15, BIT PATH DIVIDE BY 2: REG 0x15, BIT 5 5. PLL ...
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AD9863 Table 22. Serial Registers Related to the Clock Distribution Block Register Address, Register Name Bit(s) Enable IFACE2 clkout Register 0x01, Bit 2 Inv clkout (IFACE3) Register 0x01, Bit 1 Tx Inverse Sample Register 0x13, Bit 5 Interpolation Control Register ...
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Table 24 shows typical output delay times for the AD9863 in the various mode configurations. Table 24. AD9863 Rx Data Latch Timing Mode No. Mode Name Optional FD 4 HD24 5 Optional HD24 7 HD12 8 Optional ...
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... PLANE ORDERING GUIDE Model Temperature Range AD9863BCP-50 −40°C to +85°C AD9863BCPRL-50 −40°C to +85°C 1 AD9863BCPZ-50 −40°C to +85°C AD9863BCPZRL-50 1 −40°C to +85°C AD9863-50EB Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...