AD9863BCPZ-50 Analog Devices Inc, AD9863BCPZ-50 Datasheet - Page 29

IC,RF Modulator/Demodulator,LLCC,64PIN,PLASTIC

AD9863BCPZ-50

Manufacturer Part Number
AD9863BCPZ-50
Description
IC,RF Modulator/Demodulator,LLCC,64PIN,PLASTIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9863BCPZ-50

Rf Type
WLL, WLAN
Features
12-bit ADC(s), 12-bit DAC(s)
Package / Case
64-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Frequency
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9863BCPZ-50
Manufacturer:
ADI/亚德诺
Quantity:
20 000
SPI Register Map
Registers 0x00 to 0x29 of the AD9863 provide flexible operation of the device. The SPI allows access to many configurable options.
Detailed descriptions of the bit functions are found in Table 17.
Table 16. Register Map
Reg. Name
General
Clock Mode
Power-Down
RxA Power-
Down
RxB Power-
Down
Rx Power-
Down
Rx Path
Rx Path
Rx Path
Rx path
Rx Path
Tx Path
Tx Path
Tx Path
Tx Path
Tx Path
Tx Path
Tx Path
Tx Path
I/O
Configuration
I/O
Configuration
Clock
Clock
Reg.
Add
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
7
SDIO BiDir
clk_mode [2:0]
Tx analog
Rx_A analog
Rx_B analog
Rx analog bias
DAC A offset [9:2]
DAC A offset [1:0]
DAC A coarse gain control
DAC B offset [9:2]
DAC B offset [1:0]
DAC B coarse gain control
TxPGA gain [7:0]
Tx twos
complement
PLL bypass
6
LSB first
Rx_A DC bias
Rx_B DC bias
RxRef
Rx ultralow
power control
Rx ultralow
power control
TxPGA slave
enable
Rx twos
complement
5
Soft reset
DiffRef
Rx_A twos
complement
Rx_B twos
complement
Rx ultralow
power control
Rx ultralow
power control
DAC A fine gain [5:0]
DAC B fine gain [5:0]
Tx inverse
sample
Dig loop on
ADC clock div
PLL to IFACE2
Rev. A | Page 29 of 40
4
Tx digital
VREF
Rx_A Clk
Duty
Rx_B Clk
Duty
Rx ultralow
power
control
Rx ultralow
power
control
TxPGA fast
update
SpiFD/HD
Alt timing
mode
Rx ultralow
3
Rx digital
power
control
Spi
PLL Div5
Tx/ Rx
2
Enable
IFACE2
clkout
PLL power-
down
Rx ultralow
power
control
SpiB12/ 24
PLL multiplier [2:0]
PLL slow
1
Inv clkout
(IFACE3)
PLL output
disconnect
Interpolation control [1:0]
SPI IO
control
0
DAC A offset
direction
DAC B offset
direction
SpiClone
AD9863

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