AD9863BCPZ-50 Analog Devices Inc, AD9863BCPZ-50 Datasheet - Page 20

• Manufacturer Part Number: AD9863BCPZ-50
• Description: IC,RF Modulator/Demodulator,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9863BCPZ-50

• Rf Type: WLL, WLAN
• Features: 12-bit ADC(s), 12-bit DAC(s)
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9863
degradation in SNR at a given full-scale input frequency (f
due to aperture jitter (t
equation:
In the equation, the rms aperture jitter, t
sum-square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
The clock input is a digital signal that should be treated as an
analog signal with logic level threshold voltages, especially in
cases where aperture jitter may affect the dynamic range of the
AD9863. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other meth-
ods), it should be retimed by the original clock at the last step.
Power Dissipation and Standby Mode
The power dissipation of the AD9863 Rx path is proportional to
its sampling rate. The Rx path portion of the digital (DRVDD)
power dissipation is determined primarily by the strength of the
digital drivers and the load on each output bit. The digital drive
current can be calculated by
where N is the number of bits changing and C
load on the digital pins that changed.
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates, which increases with clock fre-
quency. The baseline power dissipation for either speed grade
can be reduced by asserting the ADC_LO_PWR pin, which
reduces internal ADC bias currents by half, in some cases
resulting in degraded performance.
To further reduce power consumption of the ADC, the
ADC_LO_PWR pin can be combined with a serial programmable
register setting to configure an ultralow power mode. The
ultralow power mode reduces power consumption by a fourth
of the normal power consumption. The ultralow power mode
can be used at slower sampling frequencies or if reduced
performance is acceptable. To configure the ultralow power
mode, assert the ADC_LO_PWR pin during power-up and
write the following register settings:
Figure 49 shows the typical analog power dissipation
(ADC_AVDD = 3.3 V) for the ADC vs. sampling rate for the
normal power, low power, and ultralow power modes.
SNR degradation = 20 log [(½)πF
I
DRVDD
Register 0x08
Register 0x09
Register 0x0A
= V
DRVDD
× C
A
LOAD
), can be calculated with the following
× f
(MSB) 0000 1100
(MSB) 0111 0000
(MSB) 0111 0000
CLOCK
× N
IN
t
A
A
)]
, represents the root-
LOAD
is the average
INPUT
Rev. A| Page 20 of 40
),
Either of the ADCs in the AD9863 Rx path can be placed in
standby mode independently by writing to the appropriate SPI
register bits in Register 3, Register 4, and Register 5. The
minimum standby power is achieved when both channels are
placed in full power-down mode using the appropriate SPI
register bits in Register 3, Register 4, and Register 5. Under this
condition, the internal references are powered down. When
either or both of the channel paths are enabled after a power-
down, the wake-up time is directly related to the recharging of
the REFT and REFB decoupling capacitors and the duration of
the power-down. Typically, it takes approximately 5 ms to
restore full operation with fully discharged 0.1 µF and 10 µF
decoupling capacitors on REFT and REFB.
Tx PATH BLOCK
The AD9863 transmit (Tx) path includes dual interpolating
12-bit current output DACs that can be operated independently
or can be coupled to form a complex spectrum in an image
reject transmit architecture. Each channel includes two FIR
filters, making the AD9863 capable of 1×, 2×, or 4× interpola-
tion. High speed input and output data rates can be achieved
within the limitations listed in Table 9.
Table 9. AD9863 Tx Path Maximum Data Rate
Interpolation
Rate
1×
2×
4×
By using the dual DAC outputs to form a complex signal, an
external analog quadrature modulator, such as the Analog
Devices AD8349, can enable an image rejection architecture.
(Note: the AD9863 evaluation board includes a quadrature
modulator in the Tx path that accommodates the AD8345,
AD8346, and AD8349 footprints.) To optimize the image
rejection capability as well as LO feedthrough suppression in
120
100
80
60
40
20
Figure 49. Typical Rx Path Analog Supply Current vs. Sample Rate,
0
0
ULTRALOW POWER
V
DD
5
= 3.3 V for Normal, Low, and Ultralow Power Modes
10
24-Bit Interface
Mode
FD, HD12, Clone
HD24
FD, HD12, Clone
HD24
FD, HD12, Clone
HD24
Rx PATH SAMPLING RATE (MHz)
15
20
LOW POWER
25
30
Input Data
Rate per
Channel
(MSPS)
80
160
80
80
50
50
35
NORMAL
40
45
DAC
Sampling
Rate
(MSPS)
80
160
160
160
200
200
50