AD9863BCPZ-50 Analog Devices Inc, AD9863BCPZ-50 Datasheet - Page 31

• Manufacturer Part Number: AD9863BCPZ-50
• Description: IC,RF Modulator/Demodulator,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9863BCPZ-50

• Rf Type: WLL, WLAN
• Features: 12-bit ADC(s), 12-bit DAC(s)
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Bit
Registers 0x06/0x07: Rx Path
Registers 0x08/0x09/0x0A: Rx Path
Registers 0x0B/0x0C/0x0E/0x0F:
Tx Path
Register 0x0D/0x10: Tx Path
Register 0x11: Tx Path
Register 0x12: Tx Path
Bit 6: RxREF (Power-Down)
Bit 5: DiffRef (Power-Down)
Bit 4: VREF (Power-Down)
Bit 5: Rx_A Twos Complement/
Rx_B Twos Complement
Bit 4: Rx_A Clk Duty/Rx_B Clk
Duty
Rx Ultralow Power Control Bits
DAC A/DAC B Offset
DAC A/DAC B Offset Direction
Bit 7, Bit 6: DAC A/DAC B Coarse
Gain Control
Bit 5 to Bit 0: DAC A/DAC B Fine
Gain
MSB, LSB
Bit 0 to Bit 7: TxPGA Gain
MSB, LSB
Bit 6: TxPGA Slave Enable
Description
Setting this register bit high powers down internal ADC reference circuits. Powering down these
circuits provides additional power saving over other power-down modes. The Rx path wake-up
time depends on the recovery of these references, typically of the order of a few milliseconds.
Setting this bit high powers down the ADC’s differential references, REFT and REFB. Recovery time
depends on the value of the REFT and REFB decoupling capacitors.
Setting this register bit high powers down the ADC reference circuit, VREF. Powering down the Rx
band gap reference allows an external reference to drive the VREF pin setting full-scale range of the
Rx paths.
Default data format for the Rx data is straight binary. Setting this bit high generates twos
complement data.
Setting either of these bits high enables the respective channels of the on-chip duty cycle stabilizer
(DCS) circuit to generate the internal clock for the Rx block. This option is useful for adjusting for
high speed input clocks with skewed duty cycles. The DCS mode can be used with ADC sampling
frequencies over 40 MHz.
Set all bits high, in combination with asserting the ADC_LO_PWR pin, to reduce the power
consumption of the Rx path by a fourth of normal Rx path power consumption.
These 10-bit, twos complement registers control a dc current offset that is combined with the Tx A
or Tx B output signal. An offset current of up to ±12% IOUTFS (2.4 mA for a 20 mA full-scale output)
can be applied to either differential pin on each channel. The offset current can be used to
compensate for offsets that are present in an external mixer stage, reducing LO leakage at its
output. The default setting is 0x00, no offset current. The offset current magnitude is set by using
the lower nine bits. Setting the MSB high adds the offset current to the selected differential pin,
while setting the MSB low subtracts the offset value.
This bit determines to which differential output pin the offset current is applied for the selected
channel. Setting this bit low applies the offset to the negative differential pin. Setting this bit high
applies the offset to the positive differential pin.
These register bits scale the full-scale output current (IOUTFS) of either Tx channel independently.
IOUT of the Tx channels is a function of the RSET resistor, the TxPGA setting, and the coarse gain
control setting.
The DAC output curve can be adjusted fractionally through the gain trim control. Gain trim of up to
±4% can be achieved on each channel individually. The gain trim register bits are a twos
complement attention control word.
This 8-bit, straight binary (Bit 0 is the LSB, Bit 7 is the MSB) register control for the Tx programmable
gain amplifier (TxPGA). The TxPGA provides a 20 dB continuous gain range with 0.1 dB steps (linear
in dB) simultaneously to both Tx channels. By default, this register setting is 0xFF.
The TxPGA gain is controlled through register TxPGA gain setting and, by default, is updated
immediately after the register write. If this bit is set, the TxPGA gain update is synchronized with the
falling edge of a signal applied to the TxPwrDwn pin and is enabled during the wake-up from
power-down.
00
01
10
11
100000
111111
000000
000001
011111
0000 0000
1111 1111
Rev. A | Page 31 of 40
Output current scaling by 1/11
Output current scaling by ½
No output current scaling
No output current scaling
Maximum positive gain adjustment
Minimum positive gain adjustment
No adjustment (default)
Minimum negative gain adjustment
Maximum negative gain adjustment
Minimum gain scaling –20 dB
Maximum gain scaling 0 dB
AD9863