ADM693AARWZ Analog Devices Inc, ADM693AARWZ Datasheet - Page 10

• Manufacturer Part Number: ADM693AARWZ
• Description: IC,Power Supply Supervisor,CMOS,SOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Battery Backup Circuitr

Specifications of ADM693AARWZ

• Number Of Voltages Monitored: 1
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 4.4V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADM691A/ADM693A/ADM800L/M
APPLICATIONS INFORMATION
INCREASING THE DRIVE CURRENT
If the continuous output current requirements at V
250 mA or if a lower V
external PNP pass transistor may be connected in parallel with
the internal transistor. The BATT ON output can drive the
base of the external transistor via a current limiting transistor.
Using a Rechargeable Battery for Backup
If a capacitor or a rechargeable battery is used for backup, then
the charging resistor should be connected to V
eliminates the discharge path that would exist during power
down if the resistor were connected to V
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is noninverting,
hysteresis can be added simply by connecting a resistor between
the PFO output and the PFI input as shown in Figure 23. When
PFO is low, resistor R3 sinks current from the summing junction
at the PFI pin. When PFO is high, R3 sources current into the
PFI summing junction. This results in differing trip levels for the
comparator. Resistors R1 and R2 therefore set the trip point
while R3 adds hysteresis. R3 should be larger than 10 k so that
it does not cause excessive loading on the PFO output. Addi-
tional noise rejection and filtering may be achieved by adding a
capacitor from PFI to GND.
RECHARGEABLE
POWER
POWER
INPUT
INPUT
+5V
Figure 21. Increasing the Drive Current
+5V
BATTERY
BATTERY
Figure 22. Rechargeable Battery
0.1µF
0.1µF
CC
–V
V
V
V
OUT
BATT
V
CC
BATT
CC
voltage differential is desired, an
TRANSISTOR
ADM69_A
ADM800_
I =
BATT
PNP
ON
V
R
OUT
CC.
– V
R
V
V
OUT
BATT
OUT
OUT
since this
OUT
0.1µF
0.1µF
exceeds
–10–
Typical Operating Circuit
A typical operating circuit is shown in Figure 24. The circuit
features power supply monitoring, battery backup switching
and watchdog timing.
CMOS RAM is powered from V
present, this is routed to V
routed to V
if more current is required, an external PNP transistor can be
added. When V
BATT ON goes low, providing base drive for the external tran-
sistor. When V
an internal 7 . MOSFET connects the backup battery to
V
Reset Output
The internal voltage detector monitors V
RESET output to hold the microprocessor’s RESET line low
when V
RESET low for 200 ms after V
This prevents repeated toggling of RESET even if the 5 V
power drops out and recovers with each power line cycle.
Early Power Fail Detector
The input power line is monitored via a resistive potential di-
vider connected to the Power Fail Input (PFI). When the volt-
age at PFI falls below 1.25 V, the Power Fail Output (PFO)
drives the processor’s NMI input low. If a Power Fail threshold
of 7 V is set with resistors R1 and R2, the microprocessor will
have the time when V
RAM. Power supply capacitance will extend the time available.
This will allow more time for microprocessor housekeeping
tasks to be completed before power is lost.
Figure 23. Adding Hysteresis to the Power Fail Comparator
OUT
POWER
INPUT
.
R2
R1
PFO
5V
0V
CC
0V
is below the reset threshold. An internal timer holds
OUT
CC
. V
CC
is lower than V
OUT
PFI
V
is higher than V
L
1.25V
V
CC
IN
can supply up to 250 mA from V
drops below 7 V to save data into
OUT
V
M
. If V
CC
R3
OUT
(PFO)
BATT
rises above the threshold.
BATT
CC
. When 5 V power is
and the reset threshold,
fails, then V
µP NMI
and the reset threshold,
TO
V
CC
L
V
= 1 .25 +R 1
H
and generates a
= 1.25 1 +
V
MID
= 1.25
BATT
1.25 V
R 2
R 2 R 3
R 2 +R 3
R 1 +R 2
R 2
CC
is
CC
REV. 0
R 3
R 1
– 1.25
, but