ADM693AARWZ Analog Devices Inc, ADM693AARWZ Datasheet - Page 9

• Manufacturer Part Number: ADM693AARWZ
• Description: IC,Power Supply Supervisor,CMOS,SOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Battery Backup Circuitr

Specifications of ADM693AARWZ

• Number Of Voltages Monitored: 1
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 4.4V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CE Gating and RAM Write Protection
All products include memory protection circuitry which ensures
the integrity of data in memory by preventing write operations
when V
CE
of CMOS RAM. When V
lica of CE
low the reset voltage threshold, an internal gate forces CE
high, independent of CE
CE
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V
valid level. Similar protection of EEPROMs can be achieved by
using the CE
EEPROM, EAROM, or NOVRAM.
Power Fail Warning Comparator
An additional comparator is provided for early warning of fail-
ure in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.25 V reference. The Power
Fail Output (PFO) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider that
senses either the unregulated dc input to the system’s 5 V regu-
lator or the regulated 5 V output. The voltage divider ratio can
be chosen such that the voltage at PFI falls below 1.25 V several
milliseconds before the +5 V power supply falls below the reset
threshold. PFO is normally used to interrupt the microprocessor
so that data can be stored in RAM and the shut- down proce-
dure executed before power is lost.
REV. 0
RESET
IN
OUT
WDO
Figure 18d. Internal Oscillator (100 ms Watchdog)
WDI
t
t
t
1
2
3
and CE
= RESET TIME.
= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD.
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET.
CC
typically drives the CE, CS, or Write input of battery
IN
is at an invalid level. There are two additional pins,
, with a 5 ns propagation delay. When V
OUT
OUT
t
1
Figure 19. Watchdog Timing
, that control the Chip Enable or Write inputs
to drive the Store or Write inputs of an
C
OSC
t
2
IN
CC
.
is present, CE
8
7
t
1
OSC SEL
OSC IN
ADM69_A
ADM800_
t
3
OUT
is a buffered rep-
t
1
CC
CC
is at an in-
falls be-
OUT
–9–
Signal
V
V
V
GND
BATT ON
LOW LINE
OSC IN
OSC SEL
PFI
PFO
WDI
CE
CE
WDO
RESET
RESET
Table III. Input and Output Status in Battery Backup Mode
BATT
OUT
CC
OUT
IN
ADM691A/ADM693A/ADM800L/M
POWER
INPUT
Figure 20. Power Fail Comparator
R2
R1
Status
Supply Current is <1 A.
V
PMOS switch.
Switchover comparator monitors V
active switchover.
0 V.
Logic High. The open circuit voltage is equal
to V
Logic Low.
OSC IN is ignored.
OSC SEL is ignored.
The Power Fail Comparator remains active in
the battery-backup mode for V
–1.2 V. With V
forced low.
The Power Fail Comparator remains active in
the battery-backup mode for V
–1.2 V. With V
forced low.
WDI is ignored.
Logic High. The open circuit voltage is equal
to V
High Impedance.
Logic High. The open circuit voltage is equal
to V
Logic Low.
High Impedance.
POWER
OUT
INPUT
FAIL
OUT
OUT
OUT
is connected to V
.
.
.
1.25V
CC
CC
lower than this, PFO is
lower than this, PFO is
BATT
PFO
via an internal
POWER
FAIL
OUTPUT
CC
CC
CC
V
V
BATT
BATT
for