ADM693AARWZ Analog Devices Inc, ADM693AARWZ Datasheet - Page 7

• Manufacturer Part Number: ADM693AARWZ
• Description: IC,Power Supply Supervisor,CMOS,SOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Battery Backup Circuitr

Specifications of ADM693AARWZ

• Number Of Voltages Monitored: 1
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 4.4V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER FAIL RESET OUTPUT
RESET is an active low output that provides a reset signal to the
Microprocessor whenever V
falls below the reset threshold, the RESET output is forced
low. The reset voltage threshold is 4.65 V (ADM691A/
ADM800L) or 4.4 V (ADM693A/ADM800M).
On power-up RESET will remain low for 200 milliseconds after
V
for the power supply and microprocessor to stabilize. On power-
down, the RESET output remains low with V
This ensures that the microprocessor is held in a stable shut-
down condition. If RESET is required to be low for voltages be-
low 1 V, this may be achieved by connecting a pull-down resistor
on the RESET line. The resistor will help maintain RESET low
down to V
below 2 V. With battery voltages 2 V RESET will function cor-
rectly with V
This reset active time is adjustable by using an external oscillator
or by connecting an external capacitor to the OSC IN pin. Refer
to Table II.
The guaranteed minimum and maximum thresholds of the
ADM691A/ADM800L are 4.5 V and 4.75 V, while the guaran-
teed thresholds of the ADM693A/ADM800M are 4.25 V and
4.5 V. The ADM691A/ADM800L is therefore compatible with
5 V supplies with a +10%, –5% tolerance while the ADM693A/
ADM800M is compatible with 5 V
In addition to RESET an active high RESET output is provided.
This is the complement of RESET and is useful for processors
requiring an active high RESET signal.
Watchdog Timer Reset
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a reset pulse is generated. The watch-
dog timeout period may be configured for either a fixed “short”
100 ms or a “long” 1.6 second timeout period or for an adjust-
able timeout period. Note that even if the short timeout period
is selected, the first time out immediately following a reset is
1.6 sec. This is to allow additional time for the microprocessor
to regain control following a reset.
The watchdog timer is restarted at the end of reset, whether the
reset was caused by lack of activity on WDI or by V
low the reset threshold.
REV. 0
CC
rises above the appropriate reset threshold. This allows time
Figure 14. RESET Output Voltage vs. Supply
CC
CC
= 0 V. Note that this is only necessary if V
100
0%
90
10
from 0 V to +5.5 V.
1V
CC
is at an invalid level. When V
10% supplies.
400ms
CC
as low as 1 V.
CC
falling be-
BATT
is
CC
–7–
The normal (short) timeout period becomes effective following
the first transition of WDI after reset has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be is-
sued after each timeout period (1.6 seconds). The watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI). If floating, an internal resistor network biases WDI to
around 1.6 V.
Watchdog Output (WDO)
The Watchdog Output WDO provides a status output that goes
low if the watchdog timer “times out” and remains low until set
high by the next transition on the watchdog input. WDO is also
set high when V
mains high or low indefinitely, RESET and RESET will gener-
ate 200 ms pulses every 1.6 sec.
POWER FAIL
WATCHDOG
INPUT (WDI)
INPUT (PFI)
OSC SEL
OSC IN
V
BATT
CE
ADM691A/ADM693A/ADM800L/M
V
CC
IN
Figure 16. Functional Block Diagram
Figure 15. RESET Response Time
1.25V
4.65V
1
100
VOLTAGE DETECTOR = 4.4V (ADM693A/ADM800M)
0%
90
10
WATCHDOG
CC
TIMEBASE
TRANSITION DETECTOR
RESET &
1
goes below the reset threshold. If WDI re-
WATCHDOG
1V
CHIP ENABLE
CONTROL
OUTPUT
ADM691A/ADM693A
ADM800L/ADM800M
GENERATOR
RESET &
BATT ON
WATCHDOG
10µs
TIMER
RESET
WATCHDOG
OUTPUT (WDO)
POWER FAIL
OUTPUT (PFO)
LOW LINE
V
CE
RESET
OUT
OUT