CY7C1019DV33-10BVXIT Cypress Semiconductor Corp, CY7C1019DV33-10BVXIT Datasheet - Page 5

• Manufacturer Part Number: CY7C1019DV33-10BVXIT
• Description: CY7C1019DV33-10BVXIT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1019DV33-10BVXIT

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 1M (128K x 8)
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05481 Rev. *E
Switching Characteristics
Notes
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
7. t
8. t
9. At any given temperature and voltage condition, t
10. This parameter is guaranteed by design and is not tested.
11. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
12. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
Parameter
[10]
[10]
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
POWER
HZOE
[7]
, t
HZCE
gives the minimum amount of time that the power supply should be at typical V
, and t
[11, 12]
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
HZWE
CC
(typical) to the first access
are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
Over the Operating Range
[9]
[8, 9]
[8, 9]
[9]
[8, 9]
Description
HZCE
is less than t
LZCE
, t
HZOE
[6]
is less than t
CC
LZOE
values until the first memory access can be performed
, and t
HZWE
Min.
100
10
10
HZWE
and t
3
0
3
0
8
8
0
0
7
5
0
3
–10 (Industrial)
is less than t
SD
.
LZWE
for any given device.
Max.
CY7C1019DV33
10
10
10
5
5
5
5
Page 5 of 13
Unit
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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