CY7C1041DV33-10BVJXIT Cypress Semiconductor Corp, CY7C1041DV33-10BVJXIT Datasheet - Page 6

• Manufacturer Part Number: CY7C1041DV33-10BVJXIT
• Description: CY7C1041DV33-10BVJXIT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1041DV33-10BVJXIT

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 4M (256K x 16)
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC Switching Characteristics
Over the Operating Range
Notes
Document Number: 38-05473 Rev. *I
10. Automotive product information is preliminary.
11. t
12. t
13. At any given temperature and voltage condition, t
14. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write and the transition of either of
15. The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of t
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
BW
Parameter
and 30-pF load capacitance.
a high impedance state.
device.
these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
POWER
HZOE
[11]
, t
HZCE
gives the minimum amount of time that the power supply should be at typical V
, t
[14, 15]
HZBE,
V
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z
OE HIGH to high Z
CE LOW to low Z
CE HIGH to high Z
CE LOW to power-up
CE HIGH to power-down
Byte enable to data valid
Byte enable to low Z
Byte disable to high Z
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE HIGH to low Z
WE LOW to high Z
Byte enable to end of write
CC
and t
(Typical) to the first access
HZWE
[9]
are specified with a load capacitance of 5 pF as in part (c) of
Description
[13]
[13]
[12, 13]
[12, 13]
[12, 13]
HZCE
is less than t
LZCE
Min
100
10
10
, t
–
3
–
–
0
–
3
–
0
–
–
0
–
7
7
0
0
7
5
0
3
–
7
(Industrial)
HZOE
–10
is less than t
Max
10
10
10
CC
–
–
–
5
–
5
–
5
–
5
–
6
–
–
–
–
–
–
–
–
–
5
–
values until the first memory access is performed.
AC Test Loads and
LZOE
HZWE
, t
(Automotive-A)
HZBE
and t
Min
100
10
10
–
3
–
–
0
–
3
–
0
–
–
0
–
7
7
0
0
7
5
0
3
–
7
SD
is less than t
.
–10
Waveforms. Transition is measured when the outputs enter
Max
LZBE
10
10
10
–
–
–
5
–
5
–
5
–
5
–
6
–
–
–
–
–
–
–
–
–
5
–
[10]
, and t
HZWE
(Automotive-E)
CY7C1041DV33
Min
100
12
12
–
3
–
–
0
–
3
–
0
–
–
0
–
8
8
0
0
8
6
0
3
–
8
is less than t
–12
LZWE
Max
12
12
12
–
–
–
7
–
6
–
6
–
7
–
6
–
–
–
–
–
–
–
–
–
6
–
Page 6 of 17
[10]
for any given
Unit
OL
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/I
OH
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