CY7C4255V-15ASXC Cypress Semiconductor Corp, CY7C4255V-15ASXC Datasheet - Page 17

• Manufacturer Part Number: CY7C4255V-15ASXC
• Description: CY7C4255V-15ASXC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4255V-15ASXC

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Document Number: 38-06012 Rev. *D
Notes
26. PAF offset = m. Number of data words written into FIFO already = 8192 (m + 1) for the CY7C4255V, 16384 (m + 1) for the CY7C4265V, 32768  (m + 1) for the
27. t
28. If a read is performed on this rising edge of the read clock, there are Empty + (n1) words in the FIFO when PAE goes LOW.
29. PAF is offset = m.
30. 8192 m words in CY7C4255V, 16384 m words in CY7C4265V, 32768m words in CY7C4275V, and 65536 m words in CY7C4285V.
31. 8192 (m + 1) words in CY7C4255V, 16384 (m + 1) words in CY7C4265V, 32768 (m + 1) words in CY7C4275V, and 65536 (m + 1) words in CY7C4285V.
CY7C4275V, and 65536 (m + 1) for the CY7C4285V.
and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.
SKEW3
WCLK
RCLK
PAF
WEN
WCLK
PAE
REN
RCLK
WEN
REN
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK
[29]
Figure 14. Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
t
CLKH
(continued)
t
SKEW3
t
Figure 15. Programmable Almost Full Flag Timing
CLKH
t
ENS
[27]
t
ENH
t
CLKL
Note
Note
26
t
ENS
26
t
ENH
t
PAE synch
t
CLKL
t
PAF
t
t
ENS
ENS
FULL– M WORDS
N + 1 WORDS
IN FIFO
IN FIFO
t
ENS
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
[30]
t
PAF
t
ENH
FULL– (M+1) WORDS
Note
IN FIFO
28
t
PAE synch
[31]
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