CY7C4255V-15ASXC Cypress Semiconductor Corp, CY7C4255V-15ASXC Datasheet - Page 5

• Manufacturer Part Number: CY7C4255V-15ASXC
• Description: CY7C4255V-15ASXC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4255V-15ASXC

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. Pin Definitions - CY7C4255/65/75/85V 64-pin STQFP
Document Number: 38-06012 Rev. *D
D
Q
WEN
REN
WCLK
RCLK
WXO/HF
EF
FF
PAE
PAF
LD
FL/RT
WXI
RXI
RXO
RS
OE
V
Signal Name
CC
0–17
0–17
/SMODE
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
Read Clock
Write Expansion
Out/Half Full Flag
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Load
First Load/
Retransmit
Write Expansion
Input
Read Expansion
Input
Read Expansion
Output
Reset
Output Enable
Synchronous
Almost Empty/
Almost Full Flags
Description
IO
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Data inputs for an 18-bit bus.
Data outputs for an 18-bit bus.
Enables the WCLK input.
Enables the RCLK input.
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset
register.
Dual Mode Pin:
Single device or width expansion – Half Full status flag
Cascaded – Write Expansion Out signal, connected to WXI of next device
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO. PAE is asynchronous when V
It is synchronized to RCLK when V
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when V
It is synchronized to WCLK when V
When LD is LOW, D
programmable-flag-offset register.
Dual Mode Pin:
Cascaded – The first device in the daisy chain has FL tied to V
FL tied to V
Not Cascaded – Tied to V
by strobing RT.
Cascaded – Connected to WXO of previous device
Not Cascaded – Tied to V
Cascaded – Connected to RXO of previous device
Not Cascaded – Tied to V
Cascaded – Connected to RXI of next device
Resets device to empty condition. A reset is required before an initial read or write
operation after power up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Dual Mode Pin:
Asynchronous Almost Empty/Almost Full flags – tied to V
Synchronous Almost Empty/Almost Full flags – tied to V
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
CC
. In standard mode or width expansion, FL is tied to V
0–17
SS
(Q
SS
SS
. Retransmit function is also available in standalone mode
0–17
) are written (read) into (from) the
CC
CC
Function
/SMODE is tied to V
/SMODE is tied to V
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
CC
SS
CC
CC
SS
SS
SS
/SMODE is tied to V
/SMODE is tied to V
.
; all other devices have
.
SS
on all devices.
Page 5 of 24
CC
CC
.
.
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