DSPIC33EP256MU810-I/PF Microchip Technology, DSPIC33EP256MU810-I/PF Datasheet - Page 315

• Manufacturer Part Number: DSPIC33EP256MU810-I/PF
• Description: 100 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 14x14x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU810-I/PF

• Processor Series: DSPIC33E
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Details

19.0
 2009-2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
2: Some registers and associated bits
INTER-INTEGRATED
CIRCUIT™ (I
of the dsPIC33EPXXXMU806/810/814
and PIC24EPXXXGU810/814 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 19. “Inter-Inte-
grated Circuit™ (I
the “dsPIC33E/PIC24E Family Refer-
ence Manual”, which is available from the
Microchip
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
2
C™)
2
C™)” (DS70330) of
web
site
Preliminary
in
The
PIC24EPXXXGU810/814 family of devices contain two
Inter-Integrated Circuit (I
The I
for both Slave and Multi-Master modes of the I
communication standard, with a 16-bit interface.
The I
• The SCLx pin is clock.
• The SDAx pin is data.
The I
• I
• I
• I
• I
• Serial clock synchronization for I
• I
• IPMI support
• SMBus support
modes of operation.
master and slaves.
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
collision and arbitrates accordingly.
2
2
2
2
2
C interface supporting both Master and Slave
C Slave mode supports 7 and 10-bit address.
C Master mode supports 7 and 10-bit address.
C port allows bidirectional transfers between
C supports multi-master operation, detects bus
2
2
2
C module has a 2-pin interface:
C module offers the following key features:
C module provides complete hardware support
dsPIC33EPXXXMU806/810/814
2
C) modules: I2C1 and I2C2.
2
DS70616E-page 315
C port can be
2
C serial
and