DSPIC33EP256MU810-I/PF Microchip Technology, DSPIC33EP256MU810-I/PF Datasheet - Page 367

• Manufacturer Part Number: DSPIC33EP256MU810-I/PF
• Description: 100 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 14x14x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU810-I/PF

• Processor Series: DSPIC33E
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Details

REGISTER 22-13: UxOTGIE: USB OTG INTERRUPT ENABLE REGISTER (HOST MODE ONLY)
 2009-2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
IDIE
U-0
—
Unimplemented: Read as ‘0’
IDIE: ID Interrupt Enable bit
1 = Interrupt enabled
0 = Interrupt disabled
T1MSECIE: 1 Millisecond Timer Interrupt Enable bit
1 = Interrupt enabled
0 = Interrupt disabled
LSTATEIE: Line State Stable Interrupt Enable bit
1 = Interrupt enabled
0 = Interrupt disabled
ACTVIE: Bus Activity Interrupt Enable bit
1 = Interrupt enabled
0 = Interrupt disabled
SESVDIE: Session Valid Interrupt Enable bit
1 = Interrupt enabled
0 = Interrupt disabled
SESENDIE: B-Device Session End Interrupt Enable bit
1 = Interrupt enabled
0 = Interrupt disabled
Unimplemented: Read as ‘0’
VBUSVDIE: A-Device V
1 = Interrupt enabled
0 = Interrupt disabled
T1MSECIE
R/W-0
U-0
—
W = Writable bit
‘1’ = Bit is set
LSTATEIE
R/W-0
U-0
—
BUS
Valid Interrupt Enable bit
ACTVIE
R/W-0
U-0
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SESVDIE
R/W-0
U-0
—
SESENDIE
R/W-0
U-0
—
x = Bit is unknown
U-0
U-0
—
—
DS70616E-page 367
VBUSVDIE
R/W-0
U-0
—
bit 8
bit 0