DSPIC33FJ16MC304-E/PT Microchip Technology, DSPIC33FJ16MC304-E/PT Datasheet - Page 166

16-bit DSC, 16KB Flash,Motor,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY

DSPIC33FJ16MC304-E/PT

Manufacturer Part Number
DSPIC33FJ16MC304-E/PT
Description
16-bit DSC, 16KB Flash,Motor,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC304-E/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ16MC304-E/PTTR
DSPIC33FJ16MC304-E/PTTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ16MC304-E/PT
Manufacturer:
Microchip
Quantity:
175
Part Number:
DSPIC33FJ16MC304-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
REGISTER 15-6:
DS70283H-page 166
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-12
bit 11-8
bit 7-3
bit 2
bit 1
bit 0
U-0
U-0
Unimplemented: Read as ‘0’
SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits
1111 = 1:16 postscale
0001 = 1:2 postscale
0000 = 1:1 postscale
Unimplemented: Read as ‘0’
IUE: Immediate Update Enable bit
1 = Updates to the active PxDC registers are immediate
0 = Updates to the active PxDC registers are synchronized to the PWM time base
OSYNC: Output Override Synchronization bit
1 = Output overrides via the PxOVDCON register are synchronized to the PWM time base
0 = Output overrides via the PxOVDCON register occur on next T
UDIS: PWM Update Disable bit
1 = Updates from Duty Cycle and Period Buffer registers are disabled
0 = Updates from Duty Cycle and Period Buffer registers are enabled
U-0
U-0
PWM
x
CON2: PWM CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
U-0
U-0
U-0
U-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
R/W-0
R/W-0
IUE
SEVOPS<3:0>
CY
boundary
© 2011 Microchip Technology Inc.
x = Bit is unknown
OSYNC
R/W-0
R/W-0
R/W-0
R/W-0
UDIS
bit 8
bit 0

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