EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 147

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EP2SGX90EF1152C3

Manufacturer Part Number
EP2SGX90EF1152C3
Description
Stratix II GX
Manufacturer
Altera
Datasheet

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Figure 2–88. Stratix II GX Transmitter Channel
Altera Corporation
October 2007
refclk
Fast
PLL
Each Stratix II GX receiver channel features a DPA block for phase
detection and selection, a SERDES, a synchronizer, and a data realigner
circuit. You can bypass the dynamic phase aligner without affecting the
basic source-synchronous operation of the channel. In addition, you can
dynamically switch between using the DPA block or bypassing the block
via a control signal from the logic array.
Data from R4, R24, C4, or
direct link interconnect
Interconnect
Local
diffioclk
load_en
10
10
Stratix II GX Device Handbook, Volume 1
Dedicated
Transmitter
Interface
+
Stratix II GX Architecture
Regional or
global clock
Up to 1 Gbps
2–139

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