EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 299

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

(1)
(2)
(3)
(4)
f
f
f
TCCS
SW
Output jitter
Output t
Output t
t
DPA run length
DPA jitter tolerance
DPA lock time
I N
H S D R
H S D R D PA
DUTY
Table 4–109. High-Speed I/O Specifications for -5 Speed Grade
= f
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
frequency × W ≤ 840.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
H S D R
(data rate)
R I S E
FA L L
Symbol
(DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
/ W
W = 2 to 32 (LVDS, HyperTransport technology)
(3)
W = 1 (SERDES bypass, LVDS only)
W = 1 (SERDES used, LVDS only)
J = 4 to 10 (LVDS, HyperTransport technology)
J = 2 (LVDS, HyperTransport technology)
J = 1 (LVDS only)
All differential I/O standards
All differential I/O standards
All differential I/O standards
All differential I/O standards
Data channel peak-to-peak jitter
SPI-4
Parallel Rapid I/O
Miscellaneous
Table 4–109
grade Stratix II GX devices.
shows the high-speed I/O timing specifications for -5 speed
Conditions
0000000000
1111111111
00001111
10010000
10101010
01010101
100%
10%
25%
50%
Notes
0.44
Min
150
150
150
440
256
256
256
256
256
(1),
16
(4)
(4)
16
45
-5 Speed Grade
-
(2)
Typ
50
6,400
Max
420
500
640
840
700
500
840
200
190
290
290
55
-
Number of
repetitions
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
Unit
ps
ps
ps
ps
ps
UI
UI
%