EPF10K50SBC356-2 Altera, EPF10K50SBC356-2 Datasheet - Page 17

• Manufacturer Part Number: EPF10K50SBC356-2
• Description: FLEX 10KE
• Manufacturer: Altera

Specifications of EPF10K50SBC356-2

• Family Name: FLEX 10KE
• Number Of Usable Gates: 50000
• Number Of Logic Blocks/elements: 2880
• # Registers: 220
• # I/os (max): 220
• Frequency (max): 200MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 2880
• Ram Bits: 40960
• Device System Gates: 199000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 356
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
Figure 8. FLEX 10KE Logic Element
Chip-Wide
labctrl1
labctrl2
labctrl3
labctrl4
data1
data2
data3
data4
Reset
Look-Up
Each LAB provides four control signals with programmable inversion
that can be used in all eight LEs. Two of these signals can be used as clocks,
the other two can be used for clear/preset control. The LAB clocks can be
driven by the dedicated clock input pins, global signals, I/O signals, or
internal signals via the LAB local interconnect. The LAB preset and clear
control signals can be driven by the global signals, I/O signals, or internal
signals via the LAB local interconnect. The global control signals are
typically used for global clock, clear, or preset signals because they
provide asynchronous control with very low skew across the device. If
logic is required on a control signal, it can be generated in one or more LE
in any LAB and driven into the local interconnect of the target LAB. In
addition, the global control signals can be generated from LE outputs.
Logic Element
The LE, the smallest unit of logic in the FLEX 10KE architecture, has a
compact size that provides efficient logic utilization. Each LE contains a
four-input LUT, which is a function generator that can quickly compute
any function of four variables. In addition, each LE contains a
programmable flipflop with a synchronous clock enable, a carry chain,
and a cascade chain. Each LE drives both the local and the FastTrack
Interconnect routing structure (see
Preset
Clear/
Logic
Select
Clock
(LUT)
Table
Carry-Out
Carry-In
Chain
Carry
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Cascade-Out
Cascade-In
Cascade
Chain
Register Bypass
Figure
D
ENA
8).
CLRN
PRN
Q
Programmable
Register
FastTrack
Interconnect
LAB Local
Interconnect
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