EVAL-AD7401EDZ Analog Devices Inc, EVAL-AD7401EDZ Datasheet - Page 15

• Manufacturer Part Number: EVAL-AD7401EDZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc
• Series: iCoupler®r

Specifications of EVAL-AD7401EDZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 20M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±320 mV
• Power (typ) @ Conditions: 100mW @ 20MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: AD7401
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DIGITAL FILTER
A Sinc
filter can be implemented on an FPGA or possibly a DSP. The
following Verilog code provides an example of a Sinc
implementation on a Xylinx® Spartan-II 2.5 V FPGA. This code
can possibly be compiled for another FPGA, such as an Altera®
device. Note that the data is read on the negative clock edge in
this case, although it can be read on the positive edge if preferred.
Figure 29 shows the effect of using different decimation rates
with various filter types.
/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset,
DATA);
input
input
input
filtered*/
output [15:0] DATA;
integer location;
integer info_file;
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [15:0]
reg [7:0]
reg word_clk;
reg init;
/*Perform the Sinc ACTION*/
always @ (mdata1)
if(mdata1==0)
to a -1 for 2's comp */
else
/*ACCUMULATOR (INTEGRATOR)
Perform the accumulation (IIR) at the speed
of the modulator.
3
ip_data1 <= 0;
ip_data1 <= 1;
filter is recommended for use with the AD7401. This
mclk1;
reset;
mdata1;
/*used to clk filter*/
/*used to reset filter*/
/*ip data to be
ip_data1;
acc1;
acc2;
acc3;
acc3_d1;
acc3_d2;
diff1;
diff2;
diff3;
diff1_d;
diff2_d;
DATA;
word_count;
/*filtered op*/
/* change from a 0
3
filter
Rev. C | Page 15 of 20
Z = one sample delay
MCLKIN = modulators conversion bit rate
*/
always @ (posedge mclk1 or posedge reset)
if (reset)
else
/*DECIMATION STAGE (MCLKIN/ WORD_CLK)
*/
always @ (negedge mclk1 or posedge reset)
if (reset)
else
always @ (word_count)
/*DIFFERENTIATOR (including decimation stage)
Perform the differentiation stage (FIR) at a
lower speed.
Z = one sample delay
WORD_CLK = output word rate
*/
WORD_CLK
IP_DATA1
MCLKIN
ACC3
begin
acc1 <= 0;
acc2 <= 0;
acc3 <= 0;
end
begin
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
/*initialize acc registers on reset*/
/*perform accumulation process*/
word_count <= 0;
word_count <= word_count + 1;
word_clk <= word_count[7];
+
Z
–1
Z
Figure 27. Differentiator
Figure 26. Accumulator
+
–
ACC1+
DIFF1
+
Z
Z
–1
–
+
–
ACC2+
DIFF2
+
Z
Z
–1
AD7401
–
+
ACC3+
DIFF3