RF2052TR7 RFMD, RF2052TR7 Datasheet - Page 11

• Manufacturer Part Number: RF2052TR7
• Description: IC RF MIXER PLL/VCO 32-QFN
• Manufacturer: RFMD

Specifications of RF2052TR7

• Rf Type: UHF, VHF
• Frequency: 30MHz ~ 2.5GHz
• Number Of Mixers: 1
• Gain: -2dB
• Noise Figure: 12dB
• Secondary Attributes: Up/Down Converter
• Current - Supply: 75mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 689-1089-2

Fractional-N PLL
The IC contains a charge-pump based fractional-N phase locked loop (PLL) for controlling the three VCOs. The PLL includes
automatic calibration systems to counteract the effects of process and environmental variations, ensuring repeatable lock-
time and noise performance. The PLL is intended to use a reference frequency signal of 10MHz to 104MHz. A reference
divider (divide by 1 to divide by 7) is supplied and should be programmed to limit the frequency at the phase detector to a max-
imum of 52MHz. The reference divider bypass is controlled by bit CLK DIV_BYP, set low to enable the reference divider and set
high for divider bypass (divide by 1). The remaining three bits CLK DIV<15:13> set the reference divider value, divide by 2
(010) to 7 (111) when the reference divider is enabled.
Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the
label PLL2. For the RF2052 the default programming bank is PLL2, selected by setting the MODE pin high.
The PLL will lock the VCO to the frequency F
where N
divider value (1 to 7).
The N divider is a fractional divider, containing a dual-modulus prescaler and a digitally spur-compensated fractional sequence
generator to allow fine frequency steps. The N divider is programmed using the N and NUM bits as follows:
First determine the desired, effective N divider value, N
N(9:0) should be set to the integer part of N
Example: VCO1 operating at 2220MHz, 23.92MHz reference frequency, the desired effective divider value is:
The N value is set to 92, equal to the integer part of N
by 2
Converting N and NUM into binary results in the following:
So the registers would be programmed:
The maximum N
for a 23.92MHz reference, the frequency step size would be 1.4Hz. The minimum reference frequency that could be used to
program a frequency of 2400MHz (using VCO1) is 2400/511, 4.697MHz (approx).
DS100630
24
:
EFF
is the programmed fractional N divider value, F
EFF
is 511, and the minimum N
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N
EFF
=F
VCO
NUM=0.80936454895 * 2
NUM=1100 1111 0011 0010 1000 0100
EFF
VCO
*R / F
P2_NUM_MSB=1100 1111 0011 0010
. NUM should be set to the fractional part of N
EFF
according to:
OSC
is 15, when in fractional mode. The minimum step size is F
P2_NUM_LSB=1000 0100
P2_N=0 0101 1100
F
N
=2220 *1 / 23.92=92.80936454849.
EFF
VCO
N=0 0101 1100
EFF
EFF
, and the NUM value is set to the fractional portion of N
=N
=F
:
OSC
VCO
EFF
*F
is the reference input frequency, and R is the programmed R
*R/F
OSC
24
OSC
/R
=13,578,884.
EFF
multiplied by 2
RF2052
OSC
24
/R*2
=16777216.
EFF
multiplied
24
11 of 38
. Thus