RF2052TR7 RFMD, RF2052TR7 Datasheet - Page 16

• Manufacturer Part Number: RF2052TR7
• Description: IC RF MIXER PLL/VCO 32-QFN
• Manufacturer: RFMD

Specifications of RF2052TR7

• Rf Type: UHF, VHF
• Frequency: 30MHz ~ 2.5GHz
• Number Of Mixers: 1
• Gain: -2dB
• Noise Figure: 12dB
• Secondary Attributes: Up/Down Converter
• Current - Supply: 75mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 689-1089-2

RF2052
lowed by a ‘1’ (to indicate a read operation), followed by a seven bit address. A 1.5 bit delay is introduced before the sixteen bit
data word representing the register content is presented to the receiver.
Note that since the serial bus does not require the presence of the crystal clock, it is necessary to insert an additional rising
clock edge before the ENX line is set low to ensure the address is read correctly.
Hardware Control
Three hardware control pins are provided: ENBL, MODE, and RESETB.
ENBL Pin
The ENBL pin has two functions: to enable the analog circuits in the chip and to trigger the VCO band selection as described in
the VCO section on page 10.
As outlined in the VCO section the chip has a built-in automatic VCO band selection to tune the selected VCO to the desired fre-
quency. The band selection is initiated when the ENBL pin is taken high. Every time the frequency of the synthesizer is re-pro-
grammed, the ENBL has to be inserted high to initiate the automatic VCO band selection (VCO coarse tune).
RESETB Pin
The RESETB pin is a hardware reset control that will reset all digital circuits to their start-up state when asserted low. The
device includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to
the positive supply.
MODE Pin
The MODE pin controls which PLL programming register bank is active.
For normal operation of the RF2052 the MODE pin should be set high to select the default PLL2 programming registers. It is
possible to set the FULLD bit in the CFG1 register high. This allows the MODE pin to select either PLL1 register bank
(MODE=low) or PLL2 register bank (MODE=high). This may be useful for some applications where two LO frequencies can be
programmed into the registers then the MODE pin used to toggle between them. The ENBL pin will also need to be cycled to re-
lock the synthesizer for each frequency.
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Parameter
ENBL Pin
t1
t2
High
High
Low
Low
MODE setup time
MODE hold time
Description
REFSTBY Bit
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0
1
0
1
XO and Bias Block
Time
ENBL
MODE
>5ns
>5ns
Off
On
On
On
t1
t2
Analogue Block
Off
Off
On
On
Digital Block
On
On
On
On
DS100630