RF2052TR7 RFMD, RF2052TR7 Datasheet - Page 12

• Manufacturer Part Number: RF2052TR7
• Description: IC RF MIXER PLL/VCO 32-QFN
• Manufacturer: RFMD

Specifications of RF2052TR7

• Rf Type: UHF, VHF
• Frequency: 30MHz ~ 2.5GHz
• Number Of Mixers: 1
• Gain: -2dB
• Noise Figure: 12dB
• Secondary Attributes: Up/Down Converter
• Current - Supply: 75mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 689-1089-2

RF2052
Phase Detector and Charge Pump
The chip provides a current output to drive an external loop filter. An on-chip operational amplifier can be used to design an
active loop filter or a passive design can be implemented. The maximum charge pump output current is set by the value con-
tained in the P2_CP_DEF field and CP_LO_I.
In the default state (P2_CP_DEF=31 and CP_LO_I=0) the charge pump current (ICPset) is 120uA. If CP_LO_I is set to 1 this
current is reduced to 30uA.
The charge pump current can be altered by changing the value of P2_CP_DEF. The charge pump current is defined as:
If automatic loop bandwidth correction is enabled the charge pump current is set by the calibration algorithm based upon the
VCO gain. For more information on the VCO gain calibration, which is disabled by default, please refer to the RF205x Calibra-
tion User Guide.
The phase detector will operate with a maximum input frequency of 52MHz.
Note that for high phase detector frequencies, the divider ratio decreases. For N<28 the FLL_FACT register needs to be
changed to 00 from the default value of 01. This is to ensure correct VCO band selection.
Loop Filter
The PLL may be designed to use an active or a passive loop filter as required. The internal configuration of the chip is shown
below. If the CFG1:LF_ACT bit is asserted high, the op-amp will be enabled. If the CFG1:LF_ACT bit is asserted low, the internal
op-amp is disabled and a high impedance is presented to the LFILT1 pin. The RF205x Programming Tool software can assist
with loop filter designs. Because the op-amp is used in an inverting configuration in active mode, when the passive loop filter
mode is selected the phase-detector polarity should be inverted. For active mode, CFG1:PDP=1, for passive mode,
CFG1:PDP=0.
The charge pump output voltage compliance range is typically +0.7V to +1.5V. For applications using a passive loop filter VCO
coarse tuning must be performed regularly enough to ensure that the VCO tuning voltage falls within this compliance range at
all temperatures. The active loop filter maintains the charge pump output voltage in the center of the compliance range, and
the op-amp provides a wider VCO tuning voltage range, typical 0V to +2.4V.
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ICP= ICPset*CP_DEF / 31
LFILT1
+1.1V
+
LF_ACT=TRUE
-
LFILT2
To VCO Tuning
LFILT3
DS100630