LMX24856211EVAL National Semiconductor, LMX24856211EVAL Datasheet - Page 31

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LMX24856211EVAL

Manufacturer Part Number
LMX24856211EVAL
Description
DELTA-SIGMA LOW POWER DUAL PLL
Manufacturer
National Semiconductor
Datasheet

Specifications of LMX24856211EVAL

Lead Free Status / Rohs Status
Not Compliant
REGISTER
2.5 R4 REGISTER
This register controls the conditions for the RF PLL in Fastlock.
2.5.1 MUX[3:0] Frequency Out & Lock Detect MUX
These bits determine the output state of the Ftest/LD pin.
2.5.2 IF_P -- IF Prescaler
When this bit is set to 0, the 8/9 prescaler is used. Otherwise the 16/17 prescaler is used.
R4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ATPU
23
IF_P
0
1
22 21 20 19 18 17 16 15 14 13
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
MUX[3:0]
0
DITH
[1:0]
[1:0]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FM
DATA[19:0]
IF Prescaler
0
16/17
8/9
31
OSC_
2X
12
OSC_
OUT
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
11
CPP
IF_
10
High Impedance
CPP
RF_
Output Type
9
Open Drain
Open Drain
Open Drain
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
IF_P
Maximum Frequency
8
7 6 5 4
800 MHz
800 MHz
MUX
[3:0]
RF & IF Digital Lock
RF & IF Analog Lock
RF & IF Analog Lock
RF R Divider divided
RF N Divider divided
IF R Divider divided
IF N Divider divided
General purpose
General purpose
RF Analog Lock
RF Analog Lock
RF Digital Lock
IF Analog Lock
IF Analog Lock
output, Logical
output, Logical
IF Digital Lock
Description
“High” State
“Low” State
C3 C2 C1 C0
Disabled
3
1
Output
Detect
Detect
Detect
Detect
Detect
Detect
Detect
Detect
Detect
by 2
by 2
by 2
by 2
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2
0
1
0
0
1

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