WM8973LGEFL/RV Wolfson Microelectronics, WM8973LGEFL/RV Datasheet - Page 26

• Manufacturer Part Number: WM8973LGEFL/RV
• Description: Audio CODECs Stereo Codec with H/P Spkr
• Manufacturer: Wolfson Microelectronics

Specifications of WM8973LGEFL/RV

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8973L
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Table 13 ALC Control
PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a
limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is
ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below
87.5% of full scale. This function is automatically enabled whenever the ALC is enabled.
Note:
If ATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to
prevent clipping when long attack times are used.
R17 (11h)
ALC Control 1
R18 (12h)
ALC Control 2
R19 (13h)
ALC Control 3
REGISTER
ADDRESS
8:7
6:4
3:0
7
3:0
7:4
3:0
BIT
ALCSEL
[1:0]
MAXGAIN
[2:0]
ALCL
[3:0]
ALCZC
HLD
[3:0]
DCY
[3:0]
ATK
[3:0]
LABEL
DEFAULT
00
(OFF)
111
(+30dB)
1011
(-12dB)
0 (zero
cross
off)
0000
(0ms)
0011
(192ms)
0010
(24ms)
ALC function select
00 = ALC off (PGA gain set by register)
01 = Right channel only
10 = Left channel only
11 = Stereo (PGA registers unused)
Set Maximum Gain of PGA
111 : +30dB
110 : +24dB
….(-6dB steps)
001 : -6dB
000 : -12dB
ALC target – sets signal level at ADC
input
0000 = -28.5dB FS
0001 = -27.0dB FS
… (1.5dB steps)
1110 = -7.5dB FS
1111 = -6dB FS
ALC uses zero cross detection circuit.
ALC hold time before gain is increased.
0000 = 0ms
0001 = 2.67ms
0010 = 5.33ms
… (time doubles with every step)
1111 = 43.691s
ALC decay (gain ramp-up) time
0000 = 24ms
0001 = 48ms
0010 = 96ms
… (time doubles with every step)
1010 or higher = 24.58s
ALC attack (gain ramp-down) time
0000 = 6ms
0001 = 12ms
0010 = 24ms
… (time doubles with every step)
1010 or higher = 6.14s
Note: ensure that LINVOL and
RINVOL settings (reg. 0 and 1) are
the same before entering this mode.
DESCRIPTION
PD Rev 4.2 September 2005
Production Data
26