CS4223-BS Cirrus Logic Inc, CS4223-BS Datasheet - Page 15

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CS4223-BS

Manufacturer Part Number
CS4223-BS
Description
Audio CODECs 24-Bit 105dB Ster Cod w/o Vol. Con.
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS4223-BS

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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5. REGISTER DESCRIPTIONS - CS4224
Note: All registers are read/write in I
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
DS290F1
PDN
7
0
ADC Control (address 01h)
POWER DOWN ADC (PDN)
LEFT AND RIGHT CHANNEL HIGH PASS FILTER DEFEAT (HPDR-HPDL)
LEFT AND RIGHT CHANNEL ADC MUTING (ADMR-ADML)
CALIBRATION CONTROL (CAL)
CALIBRATION STATUS (CALP) (READ ONLY)
Function:
Function:
Function:
Function:
Default = 0
0 - Disabled
1 - Enabled
The ADC will enter a low-power state when this function is enabled.
Default = 0
0 - Disabled
1 - Enabled
The internal high-pass filter is defeated when this function is enabled. Control of the internal high-
pass filter is independent for the left and right channel.
Default = 0
0 - Disabled
1 - Enabled
The output for the selected ADC channel will be muted when this function is enabled.
Default = 0
0 - Disabled
1 - Enabled
The device will automatically perform an offset calibration when brought out of reset, which last ap-
proximately 50 ms. When this function is enabled, a rising edge on the reset line will initiate an offset
calibration.
Default = 0
0 - Calibration done
1 - Calibration in progress
HPDR
6
0
HPDL
5
0
2
C mode and write-only in SPI mode, unless otherwise noted.
ADMR
4
0
ADML
3
0
CAL
2
0
CALP
CS4223 CS4224
1
0
CLKE
0
0
15

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