CS4223-BS Cirrus Logic Inc, CS4223-BS Datasheet - Page 24

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CS4223-BS

Manufacturer Part Number
CS4223-BS
Description
Audio CODECs 24-Bit 105dB Ster Cod w/o Vol. Con.
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS4223-BS

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8. APPLICATIONS
8.1
The CS4223 is a stand-alone device controlled
through dedicated pins. The CS4224 is controlled
with an external microcontroller using the serial
control port.
8.2
As with any high resolution converter, the
CS4223/4 requires careful attention to power sup-
ply and grounding arrangements to optimize per-
formance.
recommended power arrangement with VA, VD
and VL connected to clean supplies. Decoupling
capacitors should be located as close to the device
package as possible. If desired, all supply pins
may be connected to the same supply, but a de-
coupling capacitor should still be used on each
supply pin.
8.3
The operational amplifiers in the input circuitry driv-
ing the CS4223/4 may generate a small DC offset
into the A/D converter. The CS4223/4 includes a
high pass filter after the decimator to remove any
DC offset which could result in recording a DC lev-
el, possibly yielding "clicks" when switching be-
tween devices in a multichannel system.
8.4
The recommended off-chip analog filter is either a
2nd order Butterworth or a 3rd order Butterworth, if
greater out-of-band noise filtering is desired. The
CS4223/4 DAC interpolation filter has been pre-
compensated for an external 2nd order Butter-
worth filter with a 3 dB corner at Fs, or a 3rd order
Butterworth filter with a 3 dB corner at 0.75 Fs to
provide a flat frequency response and linear phase
over the passband (see Figure 14 for Fs = 48 kHz).
If the recommended filter is not used, small fre-
quency response magnitude and phase errors will
occur. In addition to providing out-of-band noise at-
tenuation, the output filters shown in Figure 14 pro-
vide differential to single-ended conversion.
8.5
The CS4223/4 may be operated in either master
mode or slave mode. In master mode, SCLK and
24
Overview
Grounding and Power Supply
Decoupling
High Pass Filter
Analog Outputs
Master vs. Slave Mode
Figures
4
and
5
shows
the
LRCK are outputs which are internally derived from
MCLK. The device will operate in master mode
when a 47 kΩ pulldown resistor is present on SD-
OUT at startup or after reset, see Figure 5. LRCK
and SCLK are inputs to the CS4223/4 when oper-
ating in slave mode. See Figures 8-11 for the avail-
able clocking modes.
8.6
The CS4223/4 includes digital de-emphasis for 32,
44.1, or 48 kHz sample rates. The frequency re-
sponse of the de-emphasis curve, as shown in Fig-
ure 15, will scale proportionally with changes in
samples rate, Fs. The de-emphasis feature is in-
cluded to accommodate older audio recordings
that utilize pre-emphasis as a means of noise re-
duction.
De-emphasis control is achieved with the DEM1/0
pins on the CS4223 or through the DEM1-0 bits in
the DSP Port Mode Byte (#5) on the CS4224.
8.7
Upon power up, the user should hold RST = 0 for
approximately 10 ms. In this state, the control port
is reset to its default settings and the part remains
in the power down mode. At the end of RST, the
device performs an offset calibration which lasts
approximately 50 ms after which the device enters
normal operation. In the CS4224, a calibration may
also be initiated via the CAL bit in the ADC Control
Byte (#1). The CALP bit in the ADC Control Byte is
a read only bit indicating the status of the calibra-
tion.
Reset/Power Down is achieved by lowering the
RST pin causing the part to enter power down.
Once RST goes high, the control port is functional
and the desired settings should be loaded.
The CS4223/4 will also enter power down mode if
the master clock source stops for approximately
10 µs or if the LRCK is not synchronous to the
master clock. The control port will retain its current
settings.
The CS4223/4 will mute the analog outputs and
enter the power down mode if the supply drops be-
low approximately 4 volts.
De-emphasis
Power-up / Reset / Power Down
Calibration
CS4223 CS4224
DS290F1

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