CS4223-BS Cirrus Logic Inc, CS4223-BS Datasheet - Page 25

• Manufacturer Part Number: CS4223-BS
• Description: Audio CODECs 24-Bit 105dB Ster Cod w/o Vol. Con.
• Manufacturer: Cirrus Logic Inc

Specifications of CS4223-BS

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.8
The control port is used to load all the internal set-
tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference prob-
lems, the control port pins should remain static if
no operation is required.
The control port has 2 modes: SPI
the CS4224 operating as a slave device. The con-
trol port interface format is selected by the SPI/I2C
pin.
8.8.1
In SPI mode, CS is the CS4224 chip select signal,
CCLK is the control port bit clock, CDIN is the input
data line from the microcontroller and the chip ad-
dress is 0010000. All signals are inputs and data is
clocked in on the rising edge of CCLK.
Figure 6 shows the operation of the control port in
SPI mode. To write to a register, bring CS low. The
first 7 bits on CDIN form the chip address, and
must be 0010000. The eighth bit is a read/write in-
dicator (R/W), which must be low to write. Register
reading from the CS4224 is not supported in the
SPI mode. The next 8 bits form the Memory Ad-
dress Pointer (MAP), which is set to the address of
the register that is to be updated. The next 8 bits
are the data which will be placed into a register
designated by the MAP.
DS290F1
Control Port Interface (CS4224 only)
SPI Mode
®
and I
2
C
®
, with
The CS4224 has a MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is a zero, then the MAP will stay constant for
successive writes. If INCR is set to a 1, then MAP
will auto increment after each byte is written, allow-
ing block writes of successive registers. Register
reading from the CS4224 is not supported in the
SPI mode.
8.8.2
In I
is clocked into and out of the part by the clock,
SCL, with the clock to data relationship as shown
in Figure 7. There is no CS pin. Pin AD0 forms the
partial chip address and should be tied to VD or
DGND as desired. The upper 6 bits of the 7 bit ad-
dress field must be 001000. In order to communi-
cate with the CS4224, the LSB of the chip address
field (first byte sent to the CS4224) should match
the setting of the AD0 pin. The eighth bit of the ad-
dress byte is the R/W bit (high for a read, low for a
write). If the operation is a write, the next byte is the
Memory Address Pointer which selects the register
to be read or written. If the operation is a read, the
contents of the register pointed to by the Memory
Address Pointer will be output. Setting the auto in-
crement bit in MAP, allows successive reads or
writes of consecutive registers. Each byte is sepa-
rated by an acknowledge bit.
2
C mode, SDA is a bidirectional data line. Data
I
2
C Mode
CS4223 CS4224
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