CS4223-BS Cirrus Logic Inc, CS4223-BS Datasheet - Page 19

• Manufacturer Part Number: CS4223-BS
• Description: Audio CODECs 24-Bit 105dB Ster Cod w/o Vol. Con.
• Manufacturer: Cirrus Logic Inc

Specifications of CS4223-BS

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.6
5.6.1
5.6.2
5.7
5.7.1
DS290F1
Reserved
ACCR
7
0
7
0
Converter Status Report (Read Only) (address 06h)
LEFT AND RIGHT CHANNEL ACCEPTANCE BIT (ACCR-ACCL)
LEFT AND RIGHT CHANNEL ADC OUTPUT LEVEL (LVR AND LVL)
Master Clock Control (address 07h)
MASTER CLOCK CONTROL (MCK)
Function:
Function:
Function:
Note: These bits are not valid when operating in slave mode.
Default = 0
0 - Requested setting valid
1 - New setting loaded
The ACCR and ACCL bits indicate when a change in the Output Attenuator Level has occurred for
the left and right channels, respectively. The value will be high when a new setting is loaded into the
Output Attenuator Level registers. The value will return low when the requested attenuation setting
has taken effect.
Default = 000
000 - Normal output levels
001 - -6 dB level
010 - -5 dB level
011 - -4 dB level
100 - -3 dB level
101 - -2 dB level
110 - -1 dB level
111 - Clipping
The analog-to-digital converter is continually monitoring the peak digital signal output for both the left
and right channel, prior to the digital limiter. The maximum output value is stored in the LVL and LVR
bits. The LVL and LVR bits are ‘sticky’, so they are reset after each read is performed.
Default = 00
00 - XTI = 256 Fs for Master Mode
01 - XTI = 384 Fs for Master Mode
10 - XTI = 512 Fs for Master Mode
The MCK bits allow for control of the Master Clock, XTI, input frequency.
Reserved
ACCL
6
0
6
0
Reserved
LVR2
5
0
5
0
Reserved
LVR1
4
0
4
0
Reserved
LVR0
3
0
3
0
Reserved
LVL2
2
0
2
0
MCK1
LVL2
CS4223 CS4224
1
0
1
0
MCK0
LVL0
0
0
0
0
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