STA304 STMicroelectronics, STA304 Datasheet
STA304
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STA304 Summary of contents
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... MHz EXTERNAL INPUT CLOCK OR BUILT-IN INDUSTRY STANDARD XTAL OSCILLATOR. 1.0 DESCRIPTION The STA304 Digital Audio Processor is a single chip device implementing end to end digital solution for audio application. In conjunction with STA500 power bridge it gives the full digital DSP-to-power high qual- ity chain with no need for audio Digital-to-Analog con- verters between DSP and power stage ...
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... STA304 1.0 DESCRIPTION (continued) The device supports two main configurations as far as input sources: AC'97 input or IIS/SPDIF input: selection is made via a dedicated pin (AC97_MODE pin). The AC`97 can be configured to work in two different ways: 'Full Compliant' mode and 'Proprietary' mode which enables more features. The selection of the operating mode is done via a specific bit in a Vendor Reserved register (see bit 0: AC97_FC_mode in the CRA register, address 5Ah) ...
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... STA304 PIN CONNECTION (Top view) SDI_1/SDATA_OUT SDI_2/SDATA_IN LRCKI/SYNC BICKI/BIT_CLK VDD_1 GND_1 RESET AC97_MODE PIN FUNCTION PIN NAME TYPE 1 SDI_1 / SDATA_OUT I 2 SDI_2 / SDATA_IN I/O 3 LRCKI / SYNC I/O 4 BICKI / BIT_CLK I/O 5 VDD_1 6 GND_1 7 RESET I 8 AC97_MODE I 9 SDA I/O 10 SCL TEST_MODE I 13 ...
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... STA304 PIN FUNCTION (continued) PIN NAME TYPE 17 VCC 18 RXP I 19 RXN I 20 VSS 21 LFE_B O 22 LFE_A O 23 SRIGHT_B O 24 SRIGHT_A O 25 GND_3 26 VDD_3 27 RIGHT_B O 28 RIGHT_A O 29 LEFT_B O 30 LEFT_A O 31 GND_4 32 VDD_4 33 SLEFT_B O 34 SLEFT_A O 35 EAPD O 36 LRCKO I/O ...
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... STA304 ABSOLUTE MAXIMUM RATINGS Symbol V Power Supply DD V Voltage on input pins i V Voltage on output pins o T Storage Temperature stg T Operative ambient temperature op P Power Consumption Digital DD P Power Consumption Analog DA THERMAL DATA Symbol R Thermal resistance Junction to Ambient thj-amb ELECTRICAL CHARACTERISTCS (V DC OPERATING CONDITIONS ...
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... STA304 DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Low Level Input Voltage il V High Level Input Voltage ih V Low Level Output Voltage ol V High Level Output Voltage oh Note 1: Takes into account 200mV voltage drop in both supply lines Note the source/sinc current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability. ...
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... STA304 to a read request the actual value of this signal is returned, not the RAM content. Due to this fact the relative RAM register content can be incongruous. • Regs. 2Ch, 2Eh and 30h (Audio Sample Rate Control): These three registers are used to setup the sample rate when the Variable Rate Mode is enabled. In re- sponse to a read request on one of these registers the actual value returned can be either BB80h or AC44h, depending on the status of an internal hardware signal ...
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... STA304 3.0 I2S INPUT INTERFACE CONFIGURATION In order to configure the I2S input interface the Configuration Register B (CRB) can be used. Using the 3 I2SI_Align_x bits one of 6 configuration mode can be selected. Following is a table describing each one of them. MODE # of SLOTS W. LENGHT Not valid Not valid ...
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... STA304 4.0 I2S OUTPUT INTERFACE CONFIGURATION In order to configure the I2S output interface the Configuration Register B (CRB) can be used. Using the 3 I2SO_Align_x bits one of 6 configuration mode can be selected. Following is a table describing each one of them. MODE # of SLOTS W. LENGHT Not valid Not valid ...
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... The 5 DDX output (L,R,SL,SR,LFE) are ternary modulated PWM, designed to drive directly STA50X power bridge ICs or any custom discrete power. The PWM output frame is delayed from channel to channel in order to reduce the crosstalk at the stereo STA50X device at low audio dynamics. The PWM order in the STA304 is: – L – ...
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... STA304 6.0 SAMPLE RATE CONVERTER The sample rate converter resamples the selected input data source in order to send to the DSP an audio stream with a fixed frequency of 48 KHz. The following picture show the basic architecture. Figure 4. DATA_IN Fs LRCK_IN The selection between X2 Fir interpolation or direct antialiasing Filter on input data is made automatically by the threshold selector block ...
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... STA304 7.0 DAP INPUT STAGE The device provides 3 mutually exclusive input interfaces: I2S, S/PDIF and AC`97. Hereby is a small description of the characteristics for each of them and a table showing how to select it. Figure 6. I2S_SPDIF_Sel I2S S/PDIF AC97_Sel AC97 PLL_Factor PLL XTI 2 7.1 Input from I S Using this input interface a maximum of 4 channels can be sent to the DSP ...
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... STA304 This interface support 4 sampling frequencies, according to the Variable and Double Rate Audio Codec `97 specification. The following table summarize the slot usage for each one the these frequencies: Freq. Slot 3 Slot 4 Slot 6 48 Left Right Center 44.1 Left Right 88.2 * Left ...
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... STA304 Figure 7. Powerdown management EAPD (reg. 26h, bit 15) PWDN pin (reg.7EFh, bit0) (Active Low) PR5 (reg.26h, bit 13) In order to avoid any possible pop-noise while switching between the various powerdown modes a particular masking technique has been adopted to drive the actual controlling signals: as shown in the above figure the 3 powerdown requests will inform the DSP using the related bits in specific registers ...
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... STA304 10.0 BASS MANAGEMENTAND EQ The STA304 has the ability to redirect the sound to the SBW channel and to pass each channel through a 4- stage cascaded 2nd order IIR filter. With the combination of the DDX gain/compressor (CRA register bits 2-3) a dynamic EQ can be implemented. Beside that, a special Side-Firing sound can be achieved by enabling this feature available with the ready made filter topology on the surround channels ...
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... STA304 Each channel has a 4 stage cascaded 2nd order filter. The user can set each filter coefficients (see paragraph 10). The coefficient for the Left and Right channels are common, as well as the coefficients for the surrounds. There is also an input scaling factor for each channel which can be set with values from 0 to -1. The scaling factor should be set to an appropriate value that will prevent the filter going into saturation ...
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... STA304 11.0 COEFFICIENT HANDLING In order to implement the Static EQ filters and the Bass management, a RAM space for user coefficients has been included in this device: starting from address 240h (YRAM) there are bit registers available for this purpose. In order to be able to read or write into these registers an indirected addressing approach must be followed by the application software ...
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... STA304 11.3 Coefficient map Index index (hex) (decimal filter coef … … … … 19 13h 20 14h 20 Surrounds filter coef. … … 39 27h 40 28h 20 SBW filter coef. 41 29h 42 2Ah 43 2bh 44 2Ch 45 2dh … … 59 3bh 60 3Ch 3 scale in factors 61 3dh 62 3Eh 63 3Fh 6 SBW ...
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... During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of 8 bits of data. 12.1.5Data input During the data input the STA304 samples the SDA signal on the rising edge of the clock SCL. For correct device operation the SDA signal has to be stable during the rising edge of the clock and the data can change only when the SCL line is low ...
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... WRITE OPERATION Following a START condition the master sends a device select code with the RW bit set to 0. The STA304 ac- knowledges this and waits for the byte of internal address. After receiving the internal bytes address the STA304 again responds with an acknowledge. ...
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... STA304 13.0 REGISTER SUMMARY 13.1 Reset Register (add. 00h) D15 D14 D13 D12 D11 Writing any value to this register performs a register reset, which causes all registers to revert to their default values. Reading this register returns 00E4h the ID code of the part and its 3D Stereo Enhancement type (See AC'97 revision 2 ...
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... STA304 13.3 Tone Control Register (add. 08h) D15 D14 D13 D12 D11 BA3 This register support tone controls (bass and treble). The step size is 2dB. Writing a 0000h corresponds to +12dB of gain. Center frequencies (from which gains are measured) are 160Hz for Bass and 5,000Hz for Treble. ...
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... STA304 13.5 Extended Audio ID Register (add. 28h) D15 D14 D13 D12 D11 0 ID0 The Extended Audio read only register that identifies which extended audio features are supported (See AC'97 revision 2.1 specification, section A.2.1). The extended features supported are Variable Rate PCM Audio (VRA), Double- Rate PCM Audio (DRA), PCM Center (CDAC), PCM Surround (SDAC) and PCM LFE (LDAC) ...
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... STA304 13.9 Configuration Register A (CRA) : add. 5Ah D15 D14 D13 D12 D11 SRC_By DRLL_d SRC_TH SRC_TH SPDIF_ pass bg R_1 R_0 Mode BIT R/W RST NAME 0 R/W 0 AC97_FC_Mode 1 R/W 0 I2SI_DBUFF_Mode 2 R/W 0 DDX_Gain_0 3 R/W 0 DDX_Gain_1 4 R/W 1 DDX_Rst 5 R/W 1 DDX_ZD_Enable 6 R/W 1 DDX_PwrMode 7 R/W 0 PLL_Factor ...
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... STA304 Table 2. DDX gain DDX_GAIN_0 DDX Gain Compression Since a full-scale output of the GC/Vol block is mapped to full output modulation, any signal exceeding 0 dBFS at the output of the GC/Vol block will be clipped. The purpose of the compression algorithm is to reduce the gain of the system when 0 dBFS has been exceeded such that clipping does not take place, thus performing an output limiting function ...
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... STA304 13.10Configuration Register B (CRB) : add. 5Ch D15 D14 D13 D12 D11 I2SO_M I2SO_LR I2SO_LR I2SO_BC I2SO_BI SbLSb CK_Master CK_Pol K_Master CK_Pol BIT R/W RST NAME 0 R/W 1 I2SI_Align_0 1 R/W 0 I2SI_Align_1 2 R/W 0 I2SI_Align_2 3 R/W 1 I2SI_BICK_Pol 4 R/W 0 I2SI_BCK_Master 5 R/W 0 I2SI_LRCK_Pol 6 R/W 0 I2SI_LRCK_Master 7 R/W 1 I2SI_MSbLSb ...
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... STA304 13.11Phantom Center Register (add. 60h) D15 D14 D13 D12 D11 Setting bit 0 enables the phantom center channel feature. When this feature is on, the content of the center channel is split and added to the L and R channels. 13.12Static EQ and Side Firing Register (add. 70h) ...
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... These registers are specific vendor identification for the STA304. The Microsoft’s Plug and Play Vendor ID code is "ALJ". The REV7.. 0 field is for the Vendor Revision number. These are read only registers, any write request to one of these will be ignored. 28/31 D10 D9 D8 ...
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... inch TYP. MAX. MECHANICAL DATA 0.063 0.006 0.055 0.057 0.015 0.018 0.008 0.472 0.480 0.394 0.401 0.315 0.472 0.480 0.394 0.401 0.315 0.031 0.024 0.030 TQFP44 ( 1.4mm) 0.039 TQFP4410 STA304 OUTLINE AND 0.10mm .004 Seating Plane C K 0076922 D 29/31 ...
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... STA304 14.0 REVISION HISTORY Date Revision 14-Jan-2002 3 Technical Migration from ST-PRESS to EDOCS 28-Apr-2010 4 Major revision to remove "Preliminary data" status from cover page for revalidation process 30/31 Changes ...
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