SPL505YC264BT Silicon Laboratories Inc, SPL505YC264BT Datasheet - Page 2

• Manufacturer Part Number: SPL505YC264BT
• Description: Clock Generators & Support Products CK505 v0.85
• Manufacturer: Silicon Laboratories Inc

Specifications of SPL505YC264BT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.4 March 21, 2007
Pin Definitions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
PCI_0/OE#_0/2_A
VDD_PCI
PCI_1/OE#_1/4_A
PCI_2/TME
PCI_3/CFG0
PCI_4/SRC5_SEL
PCIF_0/ITP_EN
VSS_PCI
VDD_48
USB_48/FSA
VSS_48
VDD_IO
SRC0/DOT96
SRC0#/DOT96#
VSS_IO
VDD_PLL3
SRC1/LCD_100/SE1
SRC1#/LCD_100#/SE2
VSS_PLL3
VDD_PLL3_IO
SRC2/SATA
SRC2#/SATA#
VSS_SRC
SRC3/OE#_0/2_B
SRC3#/OE#_1/4_B
VDD_SRC_IO
SRC4
SRC4#
SRC5#/PCI_STOP#
Name
I/O, SE,
I/O, SE 33 MHz clock/3.3V OE# Input mappable via I2C to control either SRC 0 or
I/O, SE 33 MHz clock/3.3V OE# Input mappable via I2C to control either SRC 1 or
I/O, SE 3.3V tolerance input for overclocking enable pin 33 MHz clock.
I/O, SE 3.3V tolerant input to enable SRC5/33 MHz clock output.
I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output.
O, DIF,
O, DIF,
O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output.
O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output.
O, DIF 100 MHz Differential serial reference clocks / 100MHz SATA clock
O, DIF 100 MHz Differential serial reference clocks / 100MHz SATA clock
O, DIF 100 MHz Differential serial reference clocks.
O, DIF 100 MHz Differential serial reference clocks.
Type
PWR 3.3V Power supply for PCI PLL.
PWR 3.3V Power supply for outputs and PLL.
GND
PWR 0.7V Power supply for outputs.
GND
PWR 3.3V Power supply for PLL3
GND
PWR 0.7V Power supply for PLL3 outputs.
GND
PWR 0.7V power supply for SRC outputs.
GND
I/O,
I/O,
I/O,
PD
I/O
SE
SE
Dif
Dif
Dif
SRC 2. Default PCI0
SRC 4. Default PCI1.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifica-
tions.
3.3V tolerant input for CPU frequency selection/33 MHz clock.
Refer to DC Electrical Specifications table for Vil_PCI3/CFG0 and
Vih_PCI3/CFG0 specifications.
(sampled on the CK_PWRGD assertion)
1 = SRC5, 0 = CPU_STOP#
(sampled on the CK_PWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
Ground for outputs.
3.3V tolerant input for CPU frequency selection/fixed 48 MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifica-
tions.
Ground for outputs.
Selected via I2C default is SRC0.
Selected via I2C default is SRC0.
Ground for PLL2.
100 MHz Differential serial reference clocks/100 MHz LCD video clock/SE1
and SE2 clocks. Default SRC1
100 MHz Differential serial reference clocks/100 MHz LCD video clock/SE1
and SE2 clocks. Default SRC1
Ground for PLL3.
Ground for outputs.
100-MHz Differential serial reference clocks / 3.3V OE#_0/2_B, input,
mappable via I2C to control either SRC 0 or SRC 2
100-MHz Differential serial reference clocks / 3.3V OE#_1/4_B input,
mappable via I2C to control either SRC 1 or SRC 4. Default SRC3
3.3V tolerant input for stopping PCI and SRC outputs /100 MHz Differential
serial reference clocks.
Description
SPL505YC256BT/
SPL505YC256BS
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