SPL505YC264BT Silicon Laboratories Inc, SPL505YC264BT Datasheet - Page 4

• Manufacturer Part Number: SPL505YC264BT
• Description: Clock Generators & Support Products CK505 v0.85
• Manufacturer: Silicon Laboratories Inc

Specifications of SPL505YC264BT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.4 March 21, 2007
Frequency Select Pin (FSA, FSB, and FSC)
To achieve host clock frequency selection, apply the appro-
priate logic levels to FS_A, FS_B, and FS_C, inputs before
CK_PWRGD assertion (as seen by the clock synthesizer).
When CK_PWRGD is sampled HIGH by the clock chip
(indicating processor CK_PWRGD voltage is stable), the clock
Frequency Select Pin (FSA, FSB, and FSC)
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Table 2. Command Code Definition
FSEL_2
(6:0)
FSC
Bit
7
1
0
0
0
0
1
1
1
Input Conditions
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
FSEL_1
FSB
0
0
1
1
0
0
1
1
FSEL_0
FSA
1
1
1
0
0
0
0
1
(MHz)
CPU
100
133
166
200
266
333
400
200
(MHz)
SRC
100
(MHz)
SATA
100
Description
chip samples the FS_A, FS_B, and FS_C, input values. For all
logic levels of FS_A, FS_B, and FS_C CK_PWRGDemploys
a one-shot functionality, in that once a valid HIGH on
CK_PWRGD has been sampled, all further CK_PWRGD
FS_A, FS_B, and FS_C, transitions will be ignored, except in
test mode.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h)
.
Output Frequency
DOT96
(MHz)
96
(MHz)
USB
48
SPL505YC256BT/
SPL505YC256BS
(MHz)
33.3
PCI
Page 4 of 27
14.318
(MHz)
REF