SPL505YC256BTT Silicon Laboratories Inc, SPL505YC256BTT Datasheet - Page 11

• Manufacturer Part Number: SPL505YC256BTT
• Description: Clock Generators & Support Products CK505 v0.85
• Manufacturer: Silicon Laboratories Inc

Specifications of SPL505YC256BTT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.4 March 21, 2007
Byte 14 Control Register 14
Byte 15 Control Register 15
Byte 16 Control Register 16
Byte 17 Control Register 17
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Prog_PCI-E_EN
Prog_CPU_EN
CPU_DAF_M6
CPU_DAF_M5
CPU_DAF_M4
CPU_DAF_M3
CPU_DAF_M2
CPU_DAF_M1
CPU_DAF_M0
CPU_DAF_N7
CPU_DAF_N6
CPU_DAF_N5
CPU_DAF_N4
CPU_DAF_N3
CPU_DAF_N2
CPU_DAF_N1
CPU_DAF_N0
CPU_DAF_N8
SMSW_SEL
RESERVED
RESERVED
RESERVED
RESERVED
SMSW_EN
PCI-E_N7
PCI-E_N6
PCI-E_N5
PCI-E_N4
PCI-E_N3
PCI-E_N2
PCI-E_N1
PCI-E_N0
Name
Name
Name
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The
setting of the FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[C:A] register will be used. When it is set, the frequency ratio
stated in the FSEL[2:0] register will be used
See Byte 14 for description
If Prog_CPU_EN is set, the values programmed are in CPU_FSEL_N[8:0]
and CPU_FSEL_M[6:0] will be used to determine the CPU output
frequency. The setting of the FS_Override bit determines the frequency
ratio for CPU and other output clocks. When it is cleared, the same
frequency ratio stated in the Latched FS[C:A] register will be used. When it
is set, the frequency ratio stated in the FSEL[2:0] register will be used
If Prog_SRC_EN is set, the values programmed in SRC_DAF_N[7:0] will
be used to determine the SRC output frequency.
Enable Smooth Switching, 0 = Disabled, 1= Enabled
Smooth switch select, 0 = CPU_PLL, 1 = SRC_PLL
RESERVED
Programmable PCI-E frequency enable
0 = Disabled, 1= Enabled
Programmable CPU frequency enable
0 = Disabled, 1= Enabled
RESERVED
RESERVED
RESERVED
Description
Description
Description
SPL505YC256BT/
SPL505YC256BS
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