SPL505YC256BTT Silicon Laboratories Inc, SPL505YC256BTT Datasheet - Page 12

• Manufacturer Part Number: SPL505YC256BTT
• Description: Clock Generators & Support Products CK505 v0.85
• Manufacturer: Silicon Laboratories Inc

Specifications of SPL505YC256BTT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.4 March 21, 2007
Byte 18 Control Register 18
Table 5. Crystal Recommendations
The
SPL505YC256BS requires a parallel resonance crystal.
Substituting
SPL505YC256BT/
to operate at the wrong frequency and violate the ppm speci-
fication. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal sees must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. The common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal is
not true.
14.31818 MHz
Bit
Frequency
7
6
5
4
3
2
1
0
(Fund)
Figure 1. Crystal Capacitive Clarification
@Pup
a
0
1
0
0
0
0
0
0
series
Cut
AT
resonance
Loading Load Cap
SE1/SE2_DSC2
SE1/SE2_DSC0
Parallel
USB_DSC2
USB_DSC0
REF_DSC2
REF_DSC0
PCI_DSC2
PCI_DSC0
Name
crystal
20 pF
SPL505YC256BT/
SPL505YC256BS
causes
Drive Strength Control - DSC[2:0]
0.1 mW
(max.)
Def ault REF/Usb
Drive
Def ault PCI
the
Shunt Cap
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
(max.)
5 pF
Cs1
(Byte18)
DSC_2
Motional
0.016 pF
Figure 2. Crystal Loading Example
(max.)
1
1
1
1
0
0
0
0
Ce1
X1
Description
Ci1
Clock Chip
(Vario us B ytes)
SPL505YC256BT/
XTAL
Tolerance
SPL505YC256BS
DSC_1
35 ppm
(max.)
1
1
0
0
1
1
0
0
Page 12 of 27
Ci2
X2
Ce2
(Byte 18)
Stability
DSC_0
30 ppm
(max.)
1
0
1
0
1
0
1
0
Cs2
3 to 6p
33 pF
Trim
Pin
Strongest
2.8 pF
Trace
Strength
Weakest
Buf f er
Aging
(max.)
5 ppm