SPL505YC256BTT Silicon Laboratories Inc, SPL505YC256BTT Datasheet - Page 3

• Manufacturer Part Number: SPL505YC256BTT
• Description: Clock Generators & Support Products CK505 v0.85
• Manufacturer: Silicon Laboratories Inc

Specifications of SPL505YC256BTT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.4 March 21, 2007
Pin Definitions
Pin No.
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
SRC5/CPU_STOP#
VDD_SRC
SRC6#
SRC6
VSS_SRC
SRC7#/OE#_6
SRC7/OE#_8
VDD_SRC_IO
SRC8#/CPUT2_ITP#
SRC8/CPUC2_ITP
IO_VOUT
VDD_CPU_IO
CPU1#
CPU1
VSS_CPU
CPU0#
CPU0
VDD_CPU
CK_PWRGD/PWRDWN#
FSB/TEST_MODE
VSS_REF
XOUT
XIN
VDD_REF
REF0/FSC/TEST_SEL
SMB_DATA
SMB_CLK
(continued)
Name
O, DIF 100 MHz Differential serial reference clocks.
O, DIF 100 MHz Differential serial reference clocks.
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
O, DIF Differential CPU clock outputs.
O, DIF Differential CPU clock outputs.
O, DIF Differential CPU clock outputs.
O, DIF Differential CPU clock outputs.
O, SE 14.318 MHz Crystal output.
Type
PWR 3.3V Power supply for SRC PLL.
GND
PWR 0.7V power supply for SRC outputs.
PWR 0.7V Power supply for CPU outputs.
GND
PWR 3.3V Power supply for CPU PLL.
GND
PWR 3.3V Power supply for outputs and also maintains SMBUS registers during
I/O,
I/O,
I/O,
I/O
I/O
Dif
Dif
Dif
O
I
I
I
I
3.3V tolerant input for stopping CPU outputs/100 MHz Differential serial
reference clocks.
Ground for outputs.
100 MHz Differential serial reference clocks/3.3V OE#6 Input controlling
SRC6. Default SRC7.
100 MHz Differential serial reference clocks/3.3V OE#8 Input controlling
SRC8. Default SRC7.
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte
11 Bit3:2.
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte
11 Bit3:2.
Integrated Linear Regulator Control.
depending on the configuration set in Byte 11 Bit3:2.
depending on the configuration set in Byte 11 Bit3:2.
Ground for outputs.
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input
for asserting power down (active LOW).
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifica-
tions.
Ground for outputs.
14.318 MHz Crystal input.
power-down.
3.3V tolerant input for CPU frequency selection/fixed 14.318 clock output.
Selects test mode if pulled to V
Refer to DC Electrical Specifications table for V
fications.
SMBus compatible SDATA.
SMBus compatible SCLOCK.
IHFS_C
Note: CPU1 is an iAMT clock in iAMT mode
Note: CPU1 is an iAMT clock in iAMT mode
Description
when CK_PWRGD is asserted HIGH.
SPL505YC256BT/
SPL505YC256BS
ILFS_C
Page 3 of 27
, V
IMFS_C
, V
IHFS_C
speci-