ETHER-FAST-XP-N3 Lattice, ETHER-FAST-XP-N3 Datasheet - Page 10

• Manufacturer Part Number: ETHER-FAST-XP-N3
• Description: Ethernet ICs Ethernet MAC 10/100 Mbps
• Manufacturer: Lattice

Specifications of ETHER-FAST-XP-N3

• Product: Ethernet Controllers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Although PAUSE frames may contain the Multicast Address, Multicast filtering rules do not apply to them. If bit [3]
of the TX_RX_CTL register is set, the Rx MAC will signal the Tx MAC to stop transmitting for the duration specified
in the frame. If this bit is reset, the Rx MAC assumes the Tx MAC does not have the PAUSE capability and/or does
not wish to be paused and will not signal it to stop transmitting. In either case, the PAUSE frame is received and
transferred to the FIFO.
Statistics Vector
By default, a Statistics Vector is generated for all received frames transferred to the external FIFO. If the user wants
the Rx MAC to ignore all incoming frames, then the input signal ignore_next_pkt must be asserted. In this case, a
frame that should have been received is ignored and the Rx MAC sets the Packet Ignored bit (bit 26) of the Statis-
tics Vector.
The MAX_PKT_LEN register is programmed by the user as a threshold for setting the Long Frame bit of the Statis-
tics Vector. This value is used for Un-tagged frames only. The Receive MAC will add “4” to the value specified in this
register for all VLAN tagged frames when checking against the number of bytes received in the frame. This is
because all VLAN tagged frames have additional four bytes of data.
When a tagged frame is received, the entire VLAN tag field is stored in the VLAN_TAG register. Additionally, every
time a statistics vector is generated, some of the bits are written into the corresponding bit locations [9:1] of the
TX_RX_STS register. This is done so the user can get this information via the Host interface.
The description of the bits in the Statistics Vector bus is shown in Table 3.
Table 3. Receive Statistics Vector Description
15:0
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Long Frame. This bit is set when a frame longer than specified in the MAX_FRAME_LENGTH register is received.
Short Frame. This bit is set when a frame shorter than the value specified in the MIN_FRAME_LENGTH register is
received.
IPG Violation. This bit is set when a frame is received before the IPG timer runs out.
Preamble Shrink. This bit is asserted if the number of Preamble bytes received is not equal to seven.
Carrier Event Previously Seen.
Packet Ignored. When set, this indicates the incoming packet is to be ignored.
CRC Error. This bit is set when a frame is received with an error in the CRC field.
Length Check Error. This bit is set if the number of data bytes in the incoming frame matches the value in the
length field of the frame.
Receive OK. This bit is set if the frame is received without any error.
Multicast Address. This bit is set to indicate the received frame contains a Multicast Address.
Broadcast Address. This bit is set to indicate the received frame contains a Broadcast Address.
Dribble Nibble. This bit is set when only 4 bits of the data presented on the RS interface are valid.
Unsupported Opcode. This bit is set if the received control frame has an unsupported opcode. In this version of
the IP, only the opcode for PAUSE frame is supported.
Control Frame. This bit is set to indicate that a Control frame was received.
PAUSE Frame. This bit is set when the received Control frame contains a valid PAUSE opcode.
VLAN Tag Detected. This bit is set when the Tri-Speed MAC receives a VLAN Tagged frame.
Frame Byte Count. This contains the length of the frame that was received. The frame length includes the DA, SA,
L/T, TAG, DATA, PAD and FCS fields.
10
Description
Media Access Controller User’s Guide
10/100 and 1Gig Ethernet