ETHER-FAST-XP-N3 Lattice, ETHER-FAST-XP-N3 Datasheet - Page 6

• Manufacturer Part Number: ETHER-FAST-XP-N3
• Description: Ethernet ICs Ethernet MAC 10/100 Mbps
• Manufacturer: Lattice

Specifications of ETHER-FAST-XP-N3

• Product: Ethernet Controllers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 1. Tri-Speed Ethernet MAC Input and Output Signals (Continued)
tx_discfrm
Management Interface Signals
mdi
mdo
mdio_en
G/MII Signals
txd[7:0]
txen
txer
rxdv
rxd[7:0]
rxer
col
crs
Receive MAC Application Interface
rx_fifo_full
rx_write
rx_dbout[15:0]
rx_byten[1:0]
rx_stat_vector[31:0]
rx_stat_en
Port Name
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input
Input
Input
Input
Input
Input
Input
Active
State
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
N/A
N/A
N/A
Discard Frame . This signal is asserted at the end of a frame trans-
mit process if the Tri-Speed MAC detected an error. The possible
conditions are:
The user application normally moves the pointer to next frame in
these conditions.
Management Data Input . Used to transfer information from the
PHY to the management module.
Management Data Output . Used to transmit information from the
management module to the PHY.
Management Data Out Enable . Asserted whenever mdo is valid.
This may be used to implement a bi-directional signal for mdi and
mdo.
Transmit Data Sent to the PHY Chip. In Gigabit mode, txd[7:0]
are used with a clock rate of 125 MHz. In 10/100 mode, only
txd[3:0] are used with a clock rate of 2.5 MHz and 25 MHz
respectively
Transmit Enable. Asserted by the Tri-Speed MAC to indicate the
txd bus contains valid frame.
Transmit Error. Asserted when the Tri-Speed MAC generates a
coding error on the byte currently being transferred.
Receive Data Valid. Indicates the data on the rxd bus is valid.
Receive Data Bus. Data is driven by the PHY on these lines, and
is valid whenever rxdv is asserted.
Receive Data Error. This signal is asserted by the external PHY
device when it detects an error during frame reception.
Collision. This active- high signal indicates a collision occurred
during transmission. This signal is valid for half-duplex operation in
Fast Ethernet (10/100) mode only. Otherwise, it is ignored.
Carrier Sense. This signal, when logic high, indicates the network
has activity. Otherwise, it indicates the network is idle. This signal is
valid for half-duplex operation in Fast Ethernet (10/100) mode only.
Receive FIFO Full. This signal indicates the Rx FIFO is full and
cannot accept any more data. This is an error condition and should
never happen.
Receive FIFO Write. This signal is asserted by the Tri-Speed MAC
core to request a FIFO write.
Receive FIFO Data Output. This bus contains the data that is to
be written into the Receive FIFO.
Receive FIFO Byte Enable. Indicates which of the bytes in the
rx_dbout bus is valid.
Receive Statistics Vector. This bus indicates the events encoun-
tered during frame reception. This bus is qualified by the
rx_stat_en signal. The definition of each signal is explained in the
Receive MAC section of this user's guide.
Receive Statistics Vector Enable. When asserted, this indicates
that the contents of the rx_stat_vector bus is valid.
• A FIFO under-run
• Late collision (10/100 Mode only)
• Excessive Collisions (10/100 Mode only)
6
Media Access Controller User’s Guide
Description
10/100 and 1Gig Ethernet