ETHER-FAST-XP-N3 Lattice, ETHER-FAST-XP-N3 Datasheet - Page 3

• Manufacturer Part Number: ETHER-FAST-XP-N3
• Description: Ethernet ICs Ethernet MAC 10/100 Mbps
• Manufacturer: Lattice

Specifications of ETHER-FAST-XP-N3

• Product: Ethernet Controllers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
using the frame format. On the receiving side, the Ethernet MAC extracts the different components of a frame and
transfers them to higher applications through the FIFO interface.
The data received from the G/MII interface is first buffered until sufficient data is available to be processed by the
Receive MAC (Rx MAC). The Preamble and the Start of Frame Delimiter (SFD) information are then extracted from
the incoming frame to determine the start of a valid frame. The Receive MAC checks the address of the received
packet and validates whether the frame can be received before transferring it onto the FIFO. Only valid frames are
transferred into the FIFO. This feature has the following two benefits; the systems need not re-calculate the Frame
Check Sequence (FCS) again when the frame is being transmitted, and it also keeps the receive MAC relatively
simple. The Tri-Speed MAC however always calculates CRC to check whether the frame was received error-free or
not.
Figure 1. Un-Tagged Ethernet Frame Format
A Tagged frame includes a 4-byte VLAN Tag field, which is located between the Source Address field and the
Length/Type field. The VLAN Tag field includes the VLAN Identifier and other control information needed when
operating with Virtual Bridged LANs as described in IEEE P802.1Q.
Block Diagram
Figure 2. 10/100 and 1Gig Ethernet MAC Block Diagram
PREAMBLE
7 bytes
ignore_next_pkt
tx_sndpausreq
tx_sndpaustim
rx_stat_vector
tx_fifoempty
tx_macread
rx_fifo_error
tx_fifobyten
tx_fifoavail
tx_fifodata
tx_statvec
rx_stat_en
rx_fifo_full
rx_appclk
tx_fifoctrl
tx_fifoeof
tx_staten
tx_disfrm
rx_dbout
rx_byten
tx_done
rx_write
rx_error
reset_n
sys_clk
rx_eof
1 byte
SFD
DESTINATION
ADDRESS
Transmit MAC
6 bytes
Receive and
ADDRESS
SOURCE
6 bytes
3
Media Access Controller User’s Guide
Host Interface
LENGTH/
Management
2 bytes
TYPE
Interface
G/MII
46-1500 bytes
DATA/PAD
10/100 and 1Gig Ethernet
FRAME CHECK
SEQUENCE
hcs_n
gtx_clk
tx_clk
rx_clk
rxer
crs
txd
txen
txer
rxdv
rxd
col
hdataout_en_n
hdataout
hdatain
hwrite_n
mdio_en
mdi
4 bytes
haddr
hread_n
hready_n
mdc
mdo