DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 28

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

REF_CLKO
DCEDTES
REF_CLK
RMIIMIIS
TX_EN
TXD[0]
TXD[1]
TXD[2]
TXD[3]
NAME
G20
G19
E20
E19
A19
A20
PIN
F19
F18
F20
TYPE
O
O
O
I
I
I
Transmit Data 0 through 3(MII): TXD [3:0] is presented
synchronously with the rising edge of TX_CLK. TXD [0] is the least
significant bit of the data. When TX_EN is low the data on TXD
should be ignored.
Transmit Data 0 through 1(RMII): Two bits of data TXD [1:0]
presented synchronously with the rising edge of REF_CLK.
Transmit Enable (MII): This pin is asserted high when data TXD
[3:0] is being provided by the DS33R11. The signal is deasserted
prior to the first nibble of the next frame. This signal is synchronous
with the rising edge TX_CLK. It is asserted with the first bit of the
preamble.
Transmit Enable (RMII): When this signal is asserted, the data on
TXD [1:0] is valid. This signal is synchronous to the REF_CLK.
Reference Clock (RMII and MII): When in RMII mode, all signals
from the PHY are synchronous to this clock input for both transmit
and receive. This required clock can be up to 50MHz and should
have ±100ppm accuracy.
When in MII mode in DCE operation, the DS33R11 uses this input
to generate the RX_CLK and TX_CLK outputs as required for the
Ethernet PHY interface. When the MII interface is used with DTE
operation, this clock is not required and should be tied low.
In DCE and RMII modes, this input must have a stable clock input
before setting the RST pin high for normal operation.
Reference Clock Output (RMII and MII): A derived clock output
up to 50MHz, generated by internal division of the SYSCLKI signal.
Frequency accuracy of the REF_CLKO signal will be proportional
to the accuracy of the user-supplied SYSCLKI signal. See Section
9.1.1
DCE or DTE Selection: The user must set this pin high for DCE
Mode selection or low for DTE Mode. In DCE Mode, the DS33R11
MAC port can be directly connected to another MAC. In DCE
Mode, the Transmit clock (TX_CLK) and Receive clock (RX_CLK)
are output by the DS33R11. Note that there is no software bit
selection of DCEDTES. Note that DCE Mode is only relevant when
the MAC interface is in MII mode.
RMII or MII Selection: Set high to configure the MAC for RMII
interfacing. Set low for MII interfacing.
for more information.
28 of 344
FUNCTION