DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 62

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

9.15.3 PHY MII Management Block and MDIO Interface
The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block
communicates with the external PHY using 2-wire serial interface composed of MDC (serial clock) and MDIO for
data. The MDIO data is valid on the rising edge of the MDC clock. The Frame format for the MII Management
Interface is shown
SU.MACMIIA MII Management Address Register and data is passed through the indirect SU.MACMIID Data
Register. These indirect registers are accessed through the MAC Control Registers defined in
clock is internally generated and runs at 1.67MHz.
Figure 9-8. MII Management Frame
9.16 BERT in the Ethernet Mapper
The BERT in the Ethernet Mapper can be used for generation and detection of BERT patterns. The BERT is a
software programmable test pattern generator and monitor capable of meeting most error performance
requirements for digital transmission equipment. The following restrictions are related to the BERT:
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•
•
•
•
The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data
stream. The receive direction extracts the test pattern payload from the receive data stream, and monitors the test
pattern payload for the programmable test pattern.
BERT Features
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•
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The RDEN and TDEN are inputs that can be used to “gap” bits.
BERT will transmit even when the device is set for X.86 mode and TDEN is configured as an output.
The normal traffic flow is halted while the BERT is in operation.
If the BERT is enabled for a Serial port, it will override the normal connection.
If there is a connection overridden by the BERT, when BERT operation is terminated the normal operation is
restored.
PRBS and QRSS patterns of 2
Programmable repetitive pattern. The repetitive pattern length and pattern are programmable.
24-bit error count and 32-bit bit count registers.
Programmable bit error insertion. Errors can be inserted individually.
[length n = 1 to 32 and pattern = 0 to (2
READ
WRITE
Preamble
111...111
111...111
Figure
32 bits
9-8. The read/write control of the MII Management is accomplished through the indirect
2 bits
Start
01
01
9
-1, 2
Opco
2 bits
de
10
01
15
-1 2
Phy Adrs
PHYA[4:0]
PHYA[4:0]
5 bits
23
-1 and QRSS pattern support.
n
– 1)].
62 of 344
PHYR[4:0]
PHYR[4:0]
Phy Reg
5 bits
Aroun
2 bits
Turn
ZZ
10
d
ZZZZZZZZZ
PHYD[15:0]
bits
Data
16
Idle
Bit
Z
Z
1
Table
9-6. The MDC