PX1011A-EL1/G NXP Semiconductors, PX1011A-EL1/G Datasheet

Telecom Line Management ICs PCI EXPRESS STAND ALONE X1 PHY

PX1011A-EL1/G

Manufacturer Part Number

PX1011A-EL1/G

Description

Telecom Line Management ICs PCI EXPRESS STAND ALONE X1 PHY

Manufacturer

NXP Semiconductors

Datasheet

1.PX1011A-EL1G.pdf (32 pages)

Specifications of PX1011A-EL1/G

Product

PHY

Supply Voltage (max)

1.25 V, 3.6 V

Supply Voltage (min)

1.15 V, 1.2 V

Supply Current

0.025 A

Maximum Operating Temperature

+ 70 C

Minimum Operating Temperature

0 C

Mounting Style

SMD/SMT

Number Of Channels

Package / Case

LFBGA-81

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

PX1011A-EL1/G,557

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

PX1011A-EL1/G

Manufacturer:

KEC

Quantity:

15 562

Company:

BOSTOCK HK LIMITED

Part Number:

PX1011A-EL1/G,551

Manufacturer:

NXP Semiconductors

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

PX1011A-EL1/G,557

Manufacturer:

NXP Semiconductors

Quantity:

10 000

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1. General description

2. Features

2.1 PCI Express interface

2.2 PHY/MAC interface

The PX1011A/PX1012A is a high-performance, low-power, single-lane PCI Express

electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and

signaling. The PX1011A/1012A PCI Express PHY is compliant to the PCI Express Base

Speciﬁcation, Rev. 1.0a , and Rev. 1.1 . The PX1011A/1012A includes features such as

clock and data recovery (CDR), data serialization and de-serialization, 8b/10b encoding,

analog buffers, elastic buffer and receiver detection, and provides superior performance to

the Media Access Control (MAC) layer devices.

The PX1011A/1012A is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface.

Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE)

speciﬁcation, enhanced and adapted for off-chip applications with the introduction of a

source synchronous clock for transmit and receive data. The 8-bit data interface operates

at 250 MHz with SSTL_2 signaling. The SSTL_2 signaling is compatible with the I/O

interfaces available in FPGA products.

The PX1011A/1012A PCI Express PHY supports advanced power management

functions. The PX1011AI/PX1012AI is for the industrial temperature range ( 40 C to

+85 C).

PX1011A/PX1012A

PCI Express stand-alone X1 PHY

Rev. 02 — 18 May 2006

Compliant to PCI Express Base Speciﬁcation 1.1

Single PCI Express 2.5 Gbit/s lane

Data and clock recovery from serial stream

Serializer and De-serializer (SerDes)

Receiver detection

8b/10b coding and decoding, elastic buffer and word alignment

Supports loopback

Supports direct disparity control for use in transmitting compliance pattern

Supports lane polarity inversion

Low jitter and Bit Error Rate (BER)

Based on Intel PHY Interface for PCI Express architecture v1.0 (PIPE)

Adapted for off-chip with additional synchronous clock signals (PXPIPE)

8-bit parallel data interface for transmit and receive at 250 MHz

2.5 V SSTL_2 class I signaling

Product data sheet

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