ZL30106QDG Zarlink, ZL30106QDG Datasheet - Page 12

• Manufacturer Part Number: ZL30106QDG
• Description: SONET/SDH/PDH Network Interface 64-Pin TQFP
• Manufacturer: Zarlink

Specifications of ZL30106QDG

• Package: 64TQFP
• Power Supply Type: Analog
• Typical Supply Current: 68(Max) mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.62 V
• Maximum Operating Supply Voltage: 3.63 V

3.0
The ZL30106 is a SONET/SDH Network Interface DPLL, providing timing (clock) and synchronization (frame)
signals to SONET/SDH and PDH network interface cards. The ZL30106 supports the following applications:
Figure 1 is a functional block diagram which is described in the following sections.
3.1
The ZL30106 accepts three simultaneous reference input signals and operates on their rising edges. One of them,
the primary reference (REF0), the secondary reference (REF1) or the tertiary reference (REF2) signal, is selected
as input to the TIE Corrector Circuit based on the reference selection (REF_SEL1:0) inputs. REF0 and REF1 can
be accompanied by a 2 kHz or 8 kHz frame pulse on the REF_SYNC0 and REF_SYNC1 inputs. Input REF_SYNC0
is always associated with input REF0 while input REF_SYNC1 is always associated with input REF1.
The use of the combined REF and REF_SYNC inputs allows for a very accurate phase alignment of the output
frame pulses to the 2 kHz or 8 kHz (multi) frame pulse supplied to the REF_SYNC input. This feature supports the
implementation of line card clocks where the line card locks to the backplane clock with a filter suitable for good
tracking (high bandwidth) yet still provides a (multi) frame locked to the backplane (multi) frame.
Pin #
55
56
57
58
59
60
61
62
63
64
•
•
•
•
DS1/E1 compliant with ANSI T1.403 and Telcordia GR-1244-CORE Stratum 4/4E
Derived DS1 compliant with ITU-T G.783
DS2/DS3/E2/E3 compliant with ANSI T1.102 and ITU-T G.823
SONET/SDH compliant with ITU-T G.813 option 1 and Telcordia GR-253-CORE
Reference Select Multiplexer (MUX)
Functional Description
REF_SYNC0 REF Synchronization Frame Pulse 0 (Input). This is the 2 kHz or 8 kHz (multi) frame
REF_SYNC1 REF Synchronization Frame Pulse 1 (Input). This is the 2 kHz or 8 kHz (multi) frame
APP_SEL0
TIE_CLR
BW_SEL
Name
REF0
REF1
REF2
V
NC
DD
Reference (Input). This is one of three (REF0, REF1 and REF2) input reference sources
used for synchronization. One of seven possible frequencies may be used: 2 kHz, 8 kHz,
1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. This pin is internally
pulled down to GND.
pulse synchronization input associated with the REF0 reference. While the PLL is locked
to the REF0 input reference the output (multi) frame pulses are synchronized to this
input. This pin is internally pulled down to GND.
Reference (Input). See REF0 pin description.
pulse synchronization input associated with the REF1 reference. While the PLL is locked
to the REF1 input reference the output (multi) frame pulses are synchronized to this
input. This pin is internally pulled down to GND.
Reference (Input). See REF0 pin description.
Application Selection (Input). See APP_SEL1 pin description.
Positive Supply Voltage. +3.3 V
No internal bonding Connection. Leave unconnected.
TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE)
correction circuit resulting in a realignment of input phase with output phase.
Filter Bandwidth Selection (Input). This pin selects the bandwidth of the DPLL loop
filter, see Table 2 on page 21.
Zarlink Semiconductor Inc.
ZL30106
12
DC
nominal
Description
Data Sheet