ZL30106QDG Zarlink, ZL30106QDG Datasheet - Page 9

• Manufacturer Part Number: ZL30106QDG
• Description: SONET/SDH/PDH Network Interface 64-Pin TQFP
• Manufacturer: Zarlink

Specifications of ZL30106QDG

• Package: 64TQFP
• Power Supply Type: Analog
• Typical Supply Current: 68(Max) mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.62 V
• Maximum Operating Supply Voltage: 3.63 V

2.2
Pin #
10
12
13
14
15
16
17
18
11
1
2
3
4
5
6
7
8
9
Pin Description
MODE_SEL0 Mode Select 0 (Input). This input combined with MODE_SEL1 determines the mode of
MODE_SEL1 Mode Select 1 (Input). See MODE_SEL0 pin description.
HOLDOVER
REF_FAIL0
REF_FAIL1
REF_FAIL2
AV
V
V
Name
LOCK
TRST
GND
GND
HMS
TDO
TMS
TCK
CORE
CORE
TDI
CORE
Ground. 0 V
Positive Supply Voltage. +1.8 V
Lock Indicator (Output). This output goes to a logic high when the PLL is frequency
locked to the selected input reference.
Holdover (Output). This output goes to a logic high whenever the PLL goes into
holdover mode.
Reference 0 Failure Indicator (Output). A logic high at this pin indicates that the REF0
reference frequency has exceeded the out-of-range limit set by the APP_SEL pins or that
it is exhibiting abrupt phase or frequency changes.
Reference 1 Failure Indicator (Output). A logic high at this pin indicates that the REF1
reference frequency has exceeded the out-of-range limit set by the APP_SEL pins or that
it is exhibiting abrupt phase or frequency changes.
Reference 2 Failure Indicator (Output). A logic high at this pin indicates that the REF2
reference frequency has exceeded the out-of-range limit set by the APP_SEL pins or that
it is exhibiting abrupt phase or frequency changes.
Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge
of TCK. This pin is held in high impedance state when JTAG scan is not enabled.
Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP
controller. This pin is internally pulled up to V
left unconnected.
Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be pulsed low on power-up to ensure that
the device is in the normal functional state. This pin is internally pulled up to V
this pin is not used then it should be connected to GND.
Test Clock (Input): Provides the clock to the JTAG test logic. If this pin is not used then it
should be pulled down to GND.
Positive Supply Voltage. +1.8 V
Ground. 0 V
Positive Analog Supply Voltage. +1.8 V
Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this
pin. This pin is internally pulled up to V
unconnected.
Hitless Mode Switching (Input). The HMS input controls phase accumulation during the
transition from Holdover or Freerun mode to Normal mode on the same reference. A logic
low at this pin will cause the ZL30106 to maintain the delay stored in the TIE corrector
circuit when it transitions from Holdover or Freerun mode to Normal mode. A logic high
on this pin will cause the ZL30106 to measure a new delay for its TIE corrector circuit
thereby minimizing the output phase movement when it transitions from Holdover or
Freerun mode to Normal mode.
operation, see Table 4 on page 22.
Zarlink Semiconductor Inc.
ZL30106
9
DC
DC
nominal
nominal
Description
DD
. If this pin is not used then it should be left
DC
DD
nominal
. If this pin is not used then it should be
Data Sheet
DD
. If