ISPLSI 1016E-80LT44 LATTICE SEMICONDUCTOR, ISPLSI 1016E-80LT44 Datasheet - Page 10

• Manufacturer Part Number: ISPLSI 1016E-80LT44
• Description: CPLD ispLSI® 1000E Family 2K Gates 64 Macro Cells 84MHz EECMOS Technology 5V 44-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 1016E-80LT44

• Package: 44TQFP
• Family Name: ispLSI® 1000E
• Device System Gates: 2000
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 18.5 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 16
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 84 MHz
• Operating Temperature: 0 to 70 °C

1. Pins have dual function capability.
2. Pins have dual function capability which is software selectable.
Pin Description
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
GOE 0/IN 3
ispEN
SDI/IN 0
MODE/IN 2
SDO/IN 1
SCLK/Y2
Y0
Y1/RESET
GND
VCC
NAME
1
1
1
2
1
15,
19,
25,
29,
37,
41,
2
13
14
36
24
33
11
35
1,
12,
PIN NUMBERS
3,
7,
16,
20,
26,
30,
38,
42,
23
34
PLCC
4,
8,
17,
21,
27,
31,
39,
43,
5,
9,
18,
22,
28,
32,
40,
44,
10
6,
13,
19,
23,
31,
35,
41,
PIN NUMBERS
9,
1,
40
7
8
30
18
27
5
29
17,
6,
10,
14,
20,
24,
32,
36,
42,
TQFP
2,
39
28
11,
15,
21,
25,
33,
37,
43,
3,
12,
16,
22,
26,
34,
38,
44,
4
Input/Output Pins - These are the general purpose I/O pins used by the logic
array.
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO and
SCLK controls become active.
Input - This pin performs two functions. When ispEN is logic low, it functions
as an input pin to load programming data into the device. It is a dedicated
input pin when ispEN is logic high.SDI/IN0 also is used as one of the two
control pins for the isp state machine.
Input - This pin performs two functions. When ispEN is logic low, it functions
as a pin to control the operation of the isp state machine. It is a dedicated
input pin when ispEN is logic high.
Output/Input - This pin performs two functions. When ispEN is logic low, it
functions as an output pin to read serial shift register data. It is a dedicated
input pin when ispEN is logic high.
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. It is a dedicated clock
input when ispEN is logic high. This clock input is brought into the Clock
Distribution Network, and can optionally be routed to any GLB and/or I/O
cell on the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
This pin performs two functions:
Ground (GND)
Vcc
- Dedicated clock input. This clock input is brought into the Clock
- Active Low (0) Reset pin which resets all of the GLB and I/O registers
Distribution Network, and can optionally be routed to any GLB and/or
in the device.
I/O cell on the device.
10
Specifications ispLSI 1016E
DESCRIPTION
Table 2-0002C-16-isp