ISPLSI 1016E-80LT44 LATTICE SEMICONDUCTOR, ISPLSI 1016E-80LT44 Datasheet - Page 8

• Manufacturer Part Number: ISPLSI 1016E-80LT44
• Description: CPLD ispLSI® 1000E Family 2K Gates 64 Macro Cells 84MHz EECMOS Technology 5V 44-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 1016E-80LT44

• Package: 44TQFP
• Family Name: ispLSI® 1000E
• Device System Gates: 2000
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 18.5 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 16
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 84 MHz
• Operating Temperature: 0 to 70 °C

ispLSI 1016E Timing Model
1. Calculations are based upon timing specifications for the ispLSI 1016E-
Derivations of
Derivations of
GOE 0
Ded. In
I/O Pin
Reset
(Input)
Y1,2
Y0
t
t
t
t
t
t
#59
su
h
co
su
h
co
-0.2 ns
1.4 ns
0.6 ns
9.9 ns
2.9 ns
9.1 ns
I/O Reg Bypass
D
RST
Register
Input
#28
#22
#23 - 27
I/O Cell
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
t
t
su,
su,
Logic + Reg su - Clock (min)
(
(#22 + #30 + #37) + (#40) - (#22 + #30 + #46)
(0.3 + 1.9 + 4.4) + (0.2) - (0.3 + 1.9 + 3.2)
Clock (max) + Reg h - Logic
(
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 1.9 + 3.5) + (1.5) - (0.3 + 1.9 + 4.4)
Clock (max) + Reg co + Output
(
(#22 + #30 + #46) + (#42) + (#47 + #49)
(0.3 + 1.9 + 3.5) + (1.8) + (1.0 + 1.4)
Logic + Reg su - Clock (min)
(
(#22 + #30 + #37) + (#40) - (#54 + #42 + #56)
(0.3 + 1.9 + 4.4) + (0.2) - (1.3 + 1.8 + 0.8)
Clock (max) + Reg h - Logic
(
(#54 + #42 + #56) + (#41) - (#22 + #30 + #37)
(1.3 + 1.8 + 1.8) + (1.5) - (0.3 + 1.9 + 4.4)
Clock (max) + Reg co + Output
(
(#54 + #42 + #56) + (#42) + (#47 + #49)
(1.3 + 1.8 + 1.8) + (1.8) + (1.0 + 1.4)
Q
t
t
t
t
t
t
iobp +
iobp +
iobp +
iobp +
gy0(max) +
gy0(max) +
t
t
h and
h and
t
t
t
t
grp4 +
grp4 +
grp4 +
grp4 +
t
t
co from the Product Term Clock
co from the Clock GLB
#29, 31, 32
t
t
Loading
Distribution
gco +
gco +
GRP
Delay
#55-58
Clock
GRP
#30
#54
#53
t
t
t
t
20ptxor) + (
ptck(max)) + (
20ptxor) + (
ptck(max)) + (
t
t
gcp(max)) + (
gcp(max)) + (
t
t
gsu) - (
gsu) - (
Reg 4 PT Bypass
t
t
XOR Delays
gh) - (
Control
PTs
Feedback
#44-46
gco) + (
#36-38
20 PT
#35
#59
t
t
gh) - (
gco) + (
Comb 4 PT Bypass #34
t
t
iobp +
gy0(min) +
t
OE
RE
CK
iobp +
8
t
1
orp +
t
iobp +
GLB
t
orp +
t
Specifications ispLSI 1016E
grp4 +
t
grp4 +
t
GLB Reg Bypass
ob)
D
RST
t
t
gco +
GLB Reg
t
grp4 +
ob)
Delay
1
#39
t
#40-43
ptck(min))
t
20ptxor)
t
125
Q
gcp(min))
t
20ptxor)
Table 2-0042-16
ORP Bypass
Delay
ORP
ORP
#48
#47
#49, 50
#51, 52
I/O Cell
0491-16
(Output)
I/O Pin