ISPLSI 1016E-80LT44 LATTICE SEMICONDUCTOR, ISPLSI 1016E-80LT44 Datasheet - Page 2

• Manufacturer Part Number: ISPLSI 1016E-80LT44
• Description: CPLD ispLSI® 1000E Family 2K Gates 64 Macro Cells 84MHz EECMOS Technology 5V 44-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 1016E-80LT44

• Package: 44TQFP
• Family Name: ispLSI® 1000E
• Device System Gates: 2000
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 18.5 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 16
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 84 MHz
• Operating Temperature: 0 to 70 °C

Figure 1. ispLSI 1016E Functional Block Diagram
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put,
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source
4 mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to mini-
mize overall output switching noise.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 16 universal I/O cells by the ORP. Each ispLSI
1016E device contains two Megablocks.
Functional Block Diagram
latched
SDO/IN 1
SDI/IN 0
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
ispEN
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
input,
*Note: Y1 and RESET are multiplexed on the same pin
Megablock
output
Logic Blocks
Generic
(GLBs)
A1
A2
A3
A4
A5
A6
A7
A0
or
bi-directional
Routing
Global
(GRP)
Pool
2
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1016E device are selected using the
Clock Distribution Network. Three dedicated clock pins
(Y0, Y1 and Y2) are brought into the distribution network,
and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0
and IOCLK 1) are provided to route clocks to the GLBs
and I/O cells. The Clock Distribution Network can also be
driven from a special clock GLB (B0 on the ispLSI 1016E
device). The logic of this GLB allows the user to create an
internal clock from a combination of internal signals
within the device.
Specifications ispLSI 1016E
Distribution
Network
B7
B6
B5
B4
B3
B2
B1
B0
Clock
0139B(1a)-isp
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
GOE 0/IN 3
MODE/IN 2
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16