ISPLSI 1032E-70LTI LATTICE SEMICONDUCTOR, ISPLSI 1032E-70LTI Datasheet - Page 10

• Manufacturer Part Number: ISPLSI 1032E-70LTI
• Description: CPLD ispLSI® 1000E Family 6K Gates 128 Macro Cells 70MHz EECMOS Technology 5V 100-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 1032E-70LTI

• Package: 100TQFP
• Family Name: ispLSI® 1000E
• Device System Gates: 6000
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 17.5 ns
• Number Of User I/os: 64
• Number Of Logic Blocks/elements: 32
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 70 MHz
• Operating Temperature: -40 to 85 °C

1. Internal Timing Parameters are not tested and are for reference only.
Internal Timing Parameters
PARAM.
Outputs
t
t
t
t
t
Clocks
t
t
t
t
t
Global Reset
t
ob
sl
oen
odis
goe
gy0
gy1/2
gcp
ioy2/3
iocp
gr
49 Output Buffer Delay
50 Output Buffer Delay, Slew Limited Adder
51 I/O Cell OE to Output Enabled
52 I/O Cell OE to Output Disabled
53 Global OE
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
55 Clock Delay, Y1 or Y2 to Global GLB Clock Line
56 Clock Delay, Clock GLB to Global GLB Clock Line
57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
59 Global Reset to GLB and I/O Registers
#
DESCRIPTION
1
10
Specifications ispLSI 1032E
MIN. MAX.
1.4
2.4
0.8
0.0
0.8
–
–
–
–
–
–
-90
10.0
1.4
2.9
1.8
0.0
1.8
1.7
5.3
5.3
3.7
4.5
MIN.
1.5
2.6
0.8
0.0
0.8
–
–
–
–
–
–
-80
MAX.
10.0
1.5
3.1
1.8
0.0
1.8
2.1
5.7
5.7
4.3
4.5
MIN.
1.5
1.5
0.8
0.0
0.8
–
–
–
–
–
–
-70
MAX.
Table 2-0037B/1032E
10.0
1.5
1.5
1.8
0.0
1.8
2.6
6.2
6.2
5.8
4.6
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns